Sunday, December 13, 2009 2:39 PM,

A student writes:



	 Hello again Dr. Patt,
	 I am looking at the 2006 final exam question number four and I cannot 
	 understand why the condition codes after the two single step 
	 instruction is 100 (signifying that the negative condition bit is 
	 set). Could you please explain it to me. Thanks.
	 
	 Sincerely,
	 <<name withheld to protect the student who does not see the answer to 
	 #4>>



I think I will use this question as an opportunity to show you how to go about 
solving this type of problem.

First, you note that the PC is pointing to an ADD instruction, and then you 
note that the PC after the second instruction is very far from the PC after 
the ADD instruction.  From this you conclude that the second instruction is a 
control instruction, and not many choices could produce that value of PC.  
Then you note that R6 has been incremented by two, from which you deduce that 
the second instruction must hve been an RTI.  The RTI pops the PC and PSR.  
The popped PSR was in M[x2003].  Note that its low three bits are 100, which 
of course are the cc after the RTI completes.

Good luck on the final exam.

Yale Patt