Tue, 10 Feb 2009, 17:51

A student writes:

	
	
	Dr. Patt:

	I'm pretty sure this is not anywhere in any document this time.

	My question, does something like x7FFF + x0001 = x8000, even 
	though x8000 is not the correct result (I know n bit would 
	be set, but that's it.)



Yes, ADD R1,R2,R3 will put x8000 in R1 if R2 contains x7FFF and R3
contains x0001.  And yes, x8000 will cause the N bit to be set.

You have hit a sore nerve here.  Should we have specified an overflow bit
in the ISA?  In the interest of keeping the LC-3b as lean as possible, We 
did not.  If we had, then we would have provided logic to test the sources 
and destination to see whether V (usual name for the overflow bit, as in 
oVerflow) should be set.  We did not do that so there is no indication that 
overflow has occurred.

What if we had included a V bit?  We would still have to test it after the
ADD to know that a overflow occurred.  ...and we can just as easily (well,
not exactly JUST as easily) test the sources and destination to see if an
overflow had occurred.  So, the V bit would add convenience to the
programmer, not really a lot of functionality.

We could have also added the logic in the machine to take an exception if
this even happens, as is the case with page faults.  Many ISAs do that.
We didn't.  We will talk about exceptions in a few weeks.

For now, if you see an ADD, your simulator will source the two locations, do
the add, and write the result.  And, set NZP appropriately.

	
	
	Hopefully this is not a stupid e-mail.
	 


Nope, this is not a stupid e-mail.

	
	
	Thanks,
	<<name withheld to protect the student who is reluctant to ask>>



Good luck with lab 2.
Yale Patt