Mon, 9 Mar 2009, 02:17

A student writes:

		  
		  
        Dear professor:
        After Wednesday's lecture and discussion session I am still confused by
        the mapping from virtual memory address to physical memory address. From
        the perspective of each process, instruction only knows and uses the
        virtual memory address ranged from 0x00000000 to 0xffffffff(assuming 32
        bits address space of VAX) 



Yes, each process thinks it has a full set of memory locations.  In the case
of the VAX, not really, since those 32-bit addresses starting with 10 are
addresses in what we call System Space, and every process has the same view
of System Space.  Look at the first page of my virtual memory handout.  Also, 
in the case of the VAX, 32-bit addresses starting with 11 are not used.  That 
leaves 2 GB, and yes, each process thinks it has its own page 0, its own 
page 1, ...its own page 2^21-1 of P0 space and its own page 0, page 1, 
...page 2^21-1 of P1 space.

		  
		  
        however, in the handout presented in class(The Abstraction) virtual 
        page number is represented by bit 9 to bit 29 in virtual address. 
        Does that mean two processes could have the same virtual
        page number because each process thinks that it has full power to use
        their virtual memory address from 0x00000000 to 0xffffffff? Could you
        point out my misunderstanding?



If we replace 0x00000000 to 0xffffffff with 0x00000000 to 0x7fffffff, you 
have no misunderstanding.

What you are missing is that the two page tables P0PT and P1PT are specific
to each process, so when the physical address is being computed, the page
tables of the running process are used.  Note that these page tables are
accessed by base registers (P0BR, P1BR).  So, before process A starts running, 
its context is loaded from its process control block.  Included in the process
control block is the P0BR for that process.

Since each process has a separate page table for P0 space, each process has
a separate PTE for its page 0, and indeed, each process' PTE for its page 0
maps its page 0 to a different page frame.  There is never any confusion
since only one P0BR is active at a time, and that P0BR contains the base
address of the relevant P0PT.

What about the TLB, you might ask?  Isn't the entry in the TLB simply
page number'PTE for that page?  I could have page0'PTE_for_processA_page 0
and another entry page0'PTE_for_processB_page0.  Which would get used?
Answer: either flush the TLB on a context switch, or add a process ID to
every TLB entry.  Both techniques are used.

		  
		  
        Thanks for helping
        <<name withheld to protect the student who has too many page 0's>>



Hope the above helps.

Yale Patt