Sat, 28 Mar 2009, 02:39





A student dropped by office today, confused by problem 4.  There was indeed
ambiguity.  So, I am rewording, it as follows:


* The L1 hit rate is 0.95 for instruction references and 0.90 for data 
  references.
* The L2 hit rate is 0.85 for instruction references and 0.75 for data
  references.
* 30% of all instructions are loads and stores.
* The size of each cache block is 8 words.
* The time needed to access a cache block in L1 is 1 cycle and the time 
  needed to access a cache block in L2 is 6 cycles.
* The accesses to the caches and memory are done sequentially. If there 
  is a miss in the L1 and a hit in the L2 then the total latency is 7 cycles.
* Memory is accessed only if there is a miss in both caches.
* The width of the memory bus is one word.
* It takes one clock cycle to send an address to main memory.
* It takes 20 cycles to access the main memory.
* It takes one cycle to send one word from the memory to the processor.  Thus 
  the total latency to get a word from memory to the processor is 22 cycles.
* The bus allows sending a new address to memory in the same cycle that data 
  is sent from memory to the processor.
* Assume the data is accessible to the processor only AFTER the whole cache 
  block has been brought in from the memory, and buffered on the processor 
  chip.  The processor can then access the data independent of and during 
  the cache fill.

1. What is the average access time per instruction (assume no interleaving)?
2. What is the average access time per instruction if the main memory is 4-way 
   interleaved?
3. What is the average access time per instruction if the main memory is 8-way 
   interleaved?

Sorry I caught this so late.  Good luck with the problem set.
See you in class on Monday.

Yale Patt