Exam 2 Annotated Buzzwords

Spring 2009

Note: buzzwords marked with an asterisk (*) are annotated in the Spring 2007 and Fall 2005 Buzzwords .

NMI(Non Maskable Interrupt)

Corresponding to every interrupt level is a mask bit that can mask the interrupt so that code can run with that interrupt turned off. A non-maskable interrupt is one that we always want it to interrupt the processor if it is present. Typically, the only two interrupts that are non-maskable are machine check and power failure.

ACMP

Assymetric Chip Multiprocessor. The name given to our multi-core chip which consists of one heavyweight processor (core) and many lightweight processors.

Critical Section

name given to a segment of code that accesses a particular data structure, wherein that segment of code must complete before another thread can execute code that accesses that data structure.

FPGA

Field Programmable Gate Array. Name given to a chip consisting of an array of interconnected logic blocks, such that the function of each logic block and the interconnection of the inputs and outputs of the blocks is programmable after the chip has been installed in a system. Programming consists of specifying and then loading SRAM cells on the chip that determine the functions of each logic block and their connectivity.

Northbridge, Southbridge

name given to the buses that connect the processor chip to memory (northbridge) and I/O peripherals (southbridge)

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Intelligent I/O Device

An I/O device controller that can operate independent of the processor, once the processor has specified the actions for the I/O controller to carry out. For example, a DMA access requires the I/O controller to carry out the transfer without being instructed by the processor on an instruction by instruction basis.

Supervisor/User Cache

A method of partitioning a cache so that lines of memory accessed by the processor when running in supervisor mode compete for cache lines in one partition of the cache, and lines of memory accessed by the processor when running in user mode compete for cache lines in the other partition of the cache.

Deep pipelining

a qualitative statement about the number of stages in the pipeline. A deep pipeline is one with a relatively large number of stages.

Consistent state of the machine

term used to describe the state of a machine during the sequential in-order processing of instructions after one instruction has completed execution and before the next sequential instruction has started execution. This represents a point in execution where interrupts and exceptions can be taken.

Instruction Cache

A cache that holds only cache lines from the instruction stream.

Data Cache

A cache that holds only cache lines consisting of data.

Cache set

A set consists of all cache lines sharing the same index bits in their address. Usually thought of as a "row" in the Tag Store.

Pseudo-LRU replacement policy

one of the cache replacement policies that approximates replacing that cache line from the set that was least recently accessed. We discussed in class two such policies for 4-way set associative caches: (1) the victim, next victim policy, and (2) the three-bit per set policy that combines an LRU bit for way 1 and way 2, an LRU bit for way 3 and way 4, and a third LRU bit for deciding between the other two LRU bits.

Second level (L2) cache

a larger and slower cache that is accessed if the access to the first level cache results in a miss.

Unified L2 cache

A single L2 cache that contains both code (from the L1 instruction cache) and data (from the L1 data cache)

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Cache warm up

when a processor starts processing an executable image, the cache contains no code or data associated with that image. Warm up is that initial transient period when almost every access to the cache results in a cache miss. ...that is, until the cache becomes effective with respect to supplying instructions and/or data.

Scoreboard bit

a bit indicating whether the resource associated with that bit contains valid data.

Predicated execution

execution of an instruction that is conditioned on some predicate. The normal form of a predicated instruction is op Ri,Rj,Rk,p where p is a predicate (true or false). Ri is loaded with the result of op Rj,Rk if p is true. If p is false, the instruction is treated as a no-op.

Dynamic branch prediction

branch prediction based on decisions based on run-time information.

Amdahl's Law

observation made by Gene Amdahl that maximum speed up of a parallel processor is limited by the fraction of the problem that can not take advantage of more than one processor.

Parallelizibility

the fraction of the problem that can be assigned to as many processors as are available, such that all processors are active. If the number of processors is p, then that part of the problem can be executed in 1/p of the time it would have taken with a single processor. Also called vectorizability.

Architecture Bits

term used to describe the bits in an FPGA that particularize the function of its logic blocks and their connectivity.

Interference in branch predictor (positive and negative)

the prediction of one branch based on history information acquired for other branches. If the behavior of the two branches are correlated, then the prediction generally succeeds. The interference is positive. If the behavior of the two branches are not correlated, the prediction is usually erroneous. The interference is said to be negative.

Program Order

the order of instructions in a program as specified by the programmer or by the compiler.

compilation process

the act of translating a high level program into a machine code object module.

Full Window Stall

in an out-of order processor, the inability to add more instructions to the reservation stations because every slot is occupied by an instruction that has been fetched, decoded and renamed, but not retired.

Scalar Registers

registers that contain one value. As compared to vector registers, which contain multiple values, each of which is a component of the vector.

Address, Data and Control Wires

A bus is made up of wires. Some are used for carrying the addressed required in a transfer, some for the data being transfered, and some carry control signals to arbitrate for the bus and coordinate the transfer. BBSY, SACK, BR, BG, MSYN, SSYN are examples of control signals.

Multiplexed Address and Data Bus

A bus that uses the same wires to transmit the address, and then subsequently the data.

Inexact Numbers

a number that can not be represented exactly in the data type being used. For example, with 2's complement integers, the number 2.34 can not be represented exactly. With 64-bit floating point, the number 3.6 can not be represented exactly.

Reciprocal Approximator *

vectorizable *

I/O Processor *

Handshaking *

Striping(RAID) *

Write Buffer *

Inclusive Cache *

Cold Start Problem *

Linear Address *

Segmentation *

Machine Check *

Tag Store *

Data Store *

Cache Hit/Miss Ratio *

Temporal Locality *

Spatial Locality *

Cache line (block) *

Direct-mapped Cache *

Set-associative cache *

CAM (content associative memory) *

Fully-associative cache *

Least Recently Used (LRU) replacement policy *

Victim/Next-victim replacement policy *

Random replacement policy *

FIFO replacement policy *

Write-through cache *

Write-back cache *

Virtually-indexed Physically tagged cache *

Virtually-indexed Virtually tagged cache *

Physically-indexed physically tagged cache *

Control dependency *

Data dependency (Flow dependency) *

In-order pipeline (machine) *

Out-of-Order Execution *

Out-of-Order Commit *

In-Order Commit *

Data Forwarding (data bypass, bypass network) *

Delayed Branch *

Branch Prediction *

Two-bit counter based branch prediction *

Last-time branch predictor *

Backward-taken Forward-not-taken (BTFN) branch prediction *

Speedup *

Hardware Interlocks *

Dataflow *

Tomasulo Algorithm *

Precise exceptions *

Reservation Stations *

Register Alias Table *

Reorder Buffer *

Renaming *

Retire (commit) *

Common Data Bus *

Physical Registers *

Fire the instruction *

Vector Register *

Vector Length Register *

Vector Stride Register *

Loop Buffers *

Software Managed Cache *

Row-major order *

Column-major order *

Relatively Prime *

Vector Chaining *

Stipmining *

Asynchronous Bus *

Synchronous Bus *

Polling *

Interrupt-driven I/O *

Direct Memory Access (DMA) *

Bus arbitration *

Handshake *

Burst Mode *

Bus cycle *

Centralized Arbitration *

Distributed Arbitration *

Priority Arbitration Unit (PAU) *

Bus Master *

Bus Busy Signal *

SACK signal *

Bus Request (BR) Signal *

Bus Grant (BG) Signal *

Daisy Chain *

Master Sync (MSYNC) Signal *

Slave Sync (SSYNC) Signal *

Unit in Last Place (ULP) *

Not a Number *

Underflow *

Gradual underflow *

Error due to underflow *

Error due to inexact *

Floating Point Exceptions *

Overflow in Floating Point *

Rounding in Floating Point *

Round up, round down, round to zero, and unbiased round to nearest *

Wobble *

Binade *

Subnormal Number *