EE 360N: Lab Assignment 6 Clarifications

1. We will check the values of the internal pipeline latches generated by your simulator, so make sure you follow these conventions:

   • If the data to be loaded/stored is a byte, set DATA.SIZE to 0. Set DATA.SIZE to 1 if the data to be loaded/stored is a word.

   • A load enable signal (LD.REG or LD.CC) should be set to 1, if the instruction is supposed to write to the structure which is load-enabled by that signal. If the instruction does not write to a structure, the load-enable signal associated with that structure should be set to 0.

   • BR.OP should be set to 1, if the instruction's opcode is BR. UNCON.OP should be set to 1, if the opcode of the instruction is JMP, RET, JSR, or JSRR. TRAP.OP should be set to 1 if the opcode of the instruction is TRAP.
   • ALUK signals should be 00 for ADD, 01 for AND, 10 for XOR, 11 for PASSB. PASSB lets the ALU pass the B input to the output undisturbed.
   • BR.STALL should be set to 1 if the instruction is a control instruction.
   • LSHF1 is 1, if the output of the ADDR2MUX should be left-shifted by 1.
   • DCACHE.EN should be set to 1, if the instruction is supposed to access data memory.
   • DCACHE.RW is 0, if the memory access is a read. It is 1, if the memory access is a write.
   • For mux control signals, follow the encodings shown in the figures for the pipeline stages.
   • As mentioned in the handout, if the value of a control signal does not matter, set the signal to 0.

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2. If the D-Cache is not enabled (V.DCACHE.EN signal is 0), the data output by the D-Cache should be set to 0x0000.

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3. Control store entries corresponding to invalid opcodes (opcodes 1010 and 1011) should be set to all 0.

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4. Will you check the values in pipeline latches even if the latches are invalid?

   If the pipeline latches in a stage are invalid, our grading script is still going to check the values in the latch. The datapath of a stage performs calculations regardless of whether or not the instruction in that stage is valid (unless the valid bit is explicitly input to some logic blocks to gate the calculations). For example, even if AGEX.V is 0, the address generation logic, shifter, and the ALU will still perform calculations based on the data values in AGEX latches and control signals in AGEX.CS latch. At the end of the cycle, calculated outputs of these units will be latched into the MEM latches. Concurrently, AGEX.V is propagated to MEM.V.

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5. Because all the TRAP instruction encodings start with 1111 0000, the microinstructions in states 62 and 63 should be don't cares. However, please fill the same microinstructions into states 62 and 63 as the ones in 60 and 61 since the examples on the web say so. JMP/RET is similar to the TRAP instruction. It always starts with 1100 000, thus the microinstructions in states 49, 50 and 51 should be don't cares. However, please fill the same microinstructions into states 49, 50 and 51 as the ones in 48 for the same reason as the TRAP instruction. The JSRR should be treated as the same above. Please fill the microinstruction in state 16 into state 17.

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