1. The comments indicate the number of cycles each instruction takes:

           .ORIG X3000
   AND R0, R0, #0    ; 9 cycles
           LEA R3, NUM       ; 9 cycles
           LDW R3, R3, #0    ; 15 cycles
           LDW R1, R3, #0    ; 15 cycles
           ADD R2, R1, #0    ; 9 cycles
   LOOP    ADD R0, R0, R1    ; 9 cycles
           ADD R2, R2, #-1   ; 9 cycles
           BRP LOOP          ; 10 cycles for Taken / 9 for Not Taken
           STW R0, R3, #1    ; 15 cycles
           HALT              ; 35 cycles
   NUM     .FILL x4000
           .END

2. To calculate the square of k, the inner loop gets executed k times. The branch is taken (k-1) times and not taken one time.

   Number of cycles = 9 + 9 + 15 + 15 + 9 + (k-1)*(9 + 9 + 10) + 1*(9 + 9 + 9) + 15 + 35 = 28k + 106
3. k = 255

4. After we load the value of k, check if it is negative. If so, take the 2's complement before entering the loop.

5. k can range from -255 to +255

1. State 32. We can get rid of the LD_BEN signal altogether and always load enable the BEN register.

2. The value that is loaded into BEN in state 32 could instead be calculated in state 0, but this would add delay for calculating the next state and would probably force the cycle time to be increased.

3. A = IR[15:12]
   B = IR[11]&N + IR[10]&Z + IR[9]&P  (i.e., the old BEN signal)

1. Filled in state sequence:

   

   There are many possible state numberings, but state numbers must be chosen from 24, 34, and 36-63. The state number for C must differ from the state number for B only in the bit1 position, and bit1 must be 0 for state B. For example, if state B is 36 (100100), state C must be 38 (100110). The one-bit signal X is the Ready bit (R) from memory.

2. We need a 16-bit temporary register (T) which gets its inputs from the system bus. We need a signal LD.T (extra control signal 1) to control when to load this register. This register holds the data that is fetched from memory. We also need a mux in front of the A input of the ALU. This mux should select between SR1 and the output of the temporary register. We need a control signal for the select line of this mux (ALUMX2 - extra control signal 2).

   
   ALUMX2 = 0 selects SR1
   ALUMX2 = 1 selects T

3. Filled in microinstructions:

   

   All other signals are 0. The J bits will depend on the state numbering chosen in part (a). The J bits for states A and B must correspond to the state number for B, the J bits for state C must correspond to the state number for D, and the J bits for D must be 18 (010010). The bit encodings for control signals are the same as specified in Lab 3.

Truth table for the WE Logic:

RD = 0  WR = 1;  Byte = 0  Word = 1
WE0 = (MAR[0]') AND (R.W)
WE1 = R.W AND (MAR[0] XOR DATA.SIZE)

Truth table for the Address Control Logic:

1. MDR is 64 bits (same as addressability). We cannot tell the size of the MAR, since it depends on the number of memory locations and does not depend on the addressability (the number of bits in each location).

2. Each register (DR, SR1, and SR2) would have to be specified with five bits. With the steering bit, the total number of bits used would be 16 – leaving no bits for the opcode.