Instructions

You are encouraged to work on the problem set in groups and turn in one problem set for the entire group. Remember to put all your names on the solution sheet. Also remember to put the name of the TA in whose discussion section you would like the problem set returned to you.

Questions

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1. Given the following code:

   MUL R3, R1, R2
   ADD R5, R4, R3
   ADD R6, R4, R1
   MUL R7, R8, R9
   ADD R4, R3, R7
   MUL R10, R5, R6

   Note: Each instruction is specified with the destination register first.

   Calculate the number of cycles it takes to execute the given code on the following models:

   1. A non-pipelined machine.
   2. A pipelined machine with scoreboarding and five adders and five multipliers.
   3. A pipelined machine with scoreboarding and one adder and one multiplier.

   Note: For all machine models, use the basic instruction cycle as follows:

   • Fetch (one clock cycle)
   • Decode (one clock cycle)
   • Execute (MUL takes 6, ADD takes 4 clock cycles). The multiplier and the adder are not pipelined.
   • Write-back (one clock cycle)

   Do not forget to list any assumptions you make about the pipeline structure (e.g., data forwarding between pipeline stages). Infact, we encourage you to solve the above mentioned questions with data forwarding as well, but, you are not required to do so.

2. Suppose we have the following loop executing on a pipelined LC-3b machine.

   DOIT     STW   R1, R6, #0
            ADD   R6, R6, #2
            AND   R3, R1, R2
            BRz   EVEN
            ADD   R1, R1, #3
            ADD   R5, R5, #-1
            BRp   DOIT
   EVEN     ADD   R1, R1, #1
            ADD   R7, R7, #-1 
            BRp   DOIT

   Assume that before the loop starts, the registers have the following decimal values stored in them:

   Register	Value
   R0	0
   R1	0
   R2	1
   R3	0
   R4	0
   R5	5
   R6	4000
   R7	5

   The fetch stage takes one cycle, the decode stage also takes one cycle, the execute stage takes a variable number of cycles depending on the type of instruction (see below), and the store stage takes one cycle.

   All execution units (including the load/store unit) are fully pipelined and the following instructions that use these units take the indicated number of cycles:

   Instruction	Number of Cycles
   STW	3
   ADD	3
   AND	2
   BR	1

   Data forwarding is used wherever possible. Instructions that are dependent on the previous instructions can make use of the results produced right after the previous instruction finishes the execute stage.

   The target instruction after a branch can be fetched when the BR instruction is in ST stage. For example, the execution of an ADD instruction followed by a BR would look like:

   ADD       F | D | E1 | E2 | E3 | ST
   BR            F | D  | -  | -  | E1 | ST
   TARGET                                F  | D

   The pipeline implements “in-order execution.” A scoreboarding scheme is used as discussed in class.

   Answer the following questions:

   1. How many cycles does the above loop take to execute if no branch prediction is used?

   2. How many cycles does the above loop take to execute if all branches are predicted with 100% accuracy.

   3. How many cycles does the above loop take to execute if a static BTFN (backward taken-forward not taken) branch prediction scheme is used to predict branch directions? What is the overall branch prediction accuracy? What is the prediction accuracy for each branch?

3. A five instruction sequence executes according to Tomasulo's algorithm. Each instruction is of the form ADD DR,SR1,SR2 or MUL DR,SR1,SR2. ADDs are pipelined and take 9 cycles (F-D-E1-E2-E3-E4-E5-E6-WB). MULs are also pipelined and take 11 cycles (two extra execute stages). The microengine must wait until a result is in a register before it sources it (reads it as a source operand).

   The register file before and after the sequence are shown below (tags for “After” are ignored).

   

   1. Complete the five instruction sequence in program order in the space below. Note that we have helped you by giving you the opcode and two source operand addresses for instruction 4. (The program sequence is unique.)

      

   2. In cycle 1 instruction 1 is fetched. In cycle 2, instruction 1 is decoded and instruction 2 is fetched. In cycle 3, instruction 1 starts execution, instruction 2 is decoded, and instruction 3 is fetched.

      Assume the reservation stations are all initially empty. Put each instruction into the next available reservation station. For example, the first ADD goes into “a”. The first MUL goes into “x”. Instructions remain in the reservation stations until they are completed. Show the state of the reservation stations at the end of cycle 8.

      Note: to make it easier for the grader, when allocating source registers to reservation stations, please always have the higher numbered register be assigned to SR2.

      

   3. Show the state of the Register Alias Table (V, tag, Value) at the end of cycle 8.

      

4. Consider the following piece of code:

   for(i = 0; i < 100; i++)
     A[i] = ((B[i] * C[i]) + D[i]) / 2;

   1. Translate this code into assembly language using the following instructions in the ISA (note the number of cycles each instruction takes is shown with each instruction):

      Opcode	Operands	Number of Cycles	Description
      LEA	Ri, X	1	Ri ← address of X
      LD	Ri, Rj, Rk	11	Ri ← MEM[Rj + Rk]
      ST	Ri, Rj, Rk	11	MEM[Rj + Rk] ← Ri
      MOVI	Ri, Imm	1	Ri ← Imm
      MUL	Ri, Rj, Rk	6	Ri ← Rj × Rk
      ADD	Ri, Rj, Rk	4	Ri ← Rj + Rk
      ADD	Ri, Rj, Imm	4	Ri ← Rj + Imm
      RSHFA	Ri, Rj, amount	1	Ri ← RSHFA (Rj, amount)
      BRcc	X	1	Branch to X based on condition codes

      Assume it takes one memory location to store each element of the array. Also assume that there are 8 registers (R0-R7).

      How many cycles does it take to execute the program?

   2. Now write Cray-like vector/assembly code to perform this operation in the shortest time possible. Assume that there are 8 vector registers and the length of each vector register is 64. Use the following instructions in the vector ISA:

      Opcode	Operands	Number of Cycles	Description
      LD	Vst, #n	1	Vst ← n
      LD	Vln, #n	1	Vln ← n
      VLD	Vi, X	11, pipelined
      VST	Vi, X	11, pipelined
      Vmul	Vi, Vj, Vk	6, pipelined
      Vadd	Vi, Vj, Vk	4, pipelined
      Vrshfa	Vi, Vj, amount	1
      Vbrcc	X	1

      How many cycles does it take to execute the program on the following processors? Assume that memory is 16-way interleaved.

      1. Vector processor without chaining, 1 port to memory (1 load or store per cycle)
      2. Vector processor with chaining, 1 port to memory
      3. Vector processor with chaining, 2 read ports and 1 write port to memory

5. Little Computer Inc. is now planning to build a new computer that is more suited for scientific applications. LC-3b can be modified for such applications by replacing the data type Byte with Vector. The new computer will be called LmmVC-3 (Little 'mickey mouse' Vector Computer 3). Your job is to help us implement the datapath for LmmVC-3. LmmVC-3 ISA will support all the scalar operations that LC-3b currently supports except the LDB and STB will be replaced with VLD and VST respectively. Our datapath will need to support the following new instructions:

   

   Note: VDR means “Vector Destination Register” and VSR means “Vector Source Register.”

   MOVI

   If IR[11:9] = 000, MOVI moves the unsigned quantity amount6 to Vector Stride Register (Vstride). If IR[11:9] = 001, MOVI moves the unsigned quantity amount6 to Vector Length Register (Vlength). This instruction has already been implemented for you.

   VLD

   VLD loads a vector of length Vlength from memory into VDR. VLD uses the opcode previously used by LDB. The starting address of the vector is computed by adding the LSHF1(SEXT(offset6)) to BaseR. Subsequent addresses are obtained by adding LSHF1(ZEXT(Vstride)) to the address of the preceding vector element.

   VST

   VST writes the contents of VSR into memory. VST uses the opcode previously used by STB. Address calculation is done in the same way as for VLD.

   VADD

   If IR[4] is a 1, VADD adds two vector registers (VSR1 and VSR2) and stores the result in VDR. If IR[4] is a 0, VADD adds a scalar register (SR2) to every element of VSR and stores the result in VDR.

   VLD, VST, and VADD do not modify the content of Vstride and Vlength registers.

   The following five hardware structures have been added to LC-3b in order to implement LmmVC-3.

   • Vector Register File with eight 63-element Vector registers
   • Vector Length Register
   • Vector Stride Register
   • A third input to DRMUX containing IR[8:6]
   • Grey box A
   • Box labeled X

   These structures are shown in the LmmVC-3 datapath diagram:

   

   1. A 6-bit input to the Vector Register file has been labeled X on the datapath diagram. What is the purpose of this input? (Answer in less than 10 words )

   2. The logic structure X contains a 6-bit register and some additional logic. X has two control signals as its inputs. What are these signals used for?

   3. Grey box A contains several additional muxes on both input lines to the ALU. Complete the logic diagram of grey box A (shown below) by showing all muxes and interconnects. You will need to add new signals to the control store; be sure to clearly label them in the logic diagram.

      • Keep in mind that we will still need to support all the existing scalar operations.
      • The XOR operation in the ALU can be used to compare two values.
      • Our solution required 3 additional control signals and 6 2-to-1 muxes.
      

   4. We show the beginning of the state diagram necessary to implement VLD. Using the notation of the LC-3b State Diagram, add the states you need to implement VLD. Inside each state describe what happens in that state. You can assume that you are allowed to make any changes to the microsequencer that you find necessary. You do not have to make/show these changes. You can modify BaseR and the condition codes. Make sure your design works when Vlength equals 0. Full credit will be awarded to solutions that require no more than 7 states.

      

6. (posted - 04/26/09, NEED NOT BE TURNED IN) In class, we discussed the asynchronous finite state machine for the device controller of an input-output device within the context of a priority arbitration system. Draw the state diagram for this device controller (as drawn in lecture), identify the input and output signals, and briefly explain the function of each input and output signal.

   As mentioned in class, the finite state machine has some race conditions. Identify the race conditions and show what simple modifications can be made to eliminate them.

7. (posted - 04/26/09, NEED NOT BE TURNED IN) In class we discussed asynchronous buses with central arbitration. Our job in this problem is to design the state machine for a synchronous bus using distributed arbitration. Recall that with distributed arbitration, each device receives the Bus Request signals from all other devices, and determines whether or not it is the next Bus Master. Assume all bus transactions take exactly one cycle, and that no device may be the Bus Master for two consecutive cycles.

   Assume four devices, having priorities 1, 2, 3, and 4 respectively. Their respective controllers request the bus via asserting BR1, BR2, BR3, and BR4 respectively. Priority 4 is the highest priority.

   1. Show the interconnections required for distributed arbitration for the four devices and their controllers connected to the bus. Be sure to label each signal line and designate by arrows whether the signals are input or output with respect to the device.

   2. Is it possible for starvation to occur in this configuration? Describe the situation where this can occur.

   3. Assume each I/O Controller is implemented using a clocked finite state machine. Draw a Moore model state machine for the controller operating at priority level 2. Label each state clearly. Label all necesary inputs and outputs. You do not need to show the clock signal on the state machine diagram. State transitions are synchronized to the clock.