Buzzwords:
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segmentation
Horizontal vs Vertical Microcode
nanocode
RISC vs CISC
interlocks
Science of trade-offs
Levels of transformation
critical path (speed path) design
bread and butter design
pipelining (intra-instruction parallelism)
compile-time (static)
runtime (dynamic)
uniform vs. non-uniform decode
balanced design
performance metric (standard performance equation)
IPC (instructions per cycle)
CPI (cycles per instruction)
Interference in branch predictor (positive and negative)
Branch Prediction
Delayed Branch
Program Order
Two-bit counter based branch prediction
Last-time branch predictor
Backward-taken Forward-not-taken (BTFN) branch prediction
compile-time branch prediction
phase changes
representativeness
dynamic prediction
pattern history table
history register
2-level adaptive branch predictor
gshare branch predictor
hybrid branch predictor
perceptrorn branch precition
branch target buffer
Return Address Stack
indirect branches
speedup
memory disambiguation problem
OGehl branch precitor
L-TAGE branch predictor
Stack Machine (0 address machine, 1 address machine, etc.)
Ld/St Architecture
Micro-op Fusion
HPS model, out-of-order, wide-issue, speculative execution, branch
issue/schedule -- dispatch/issue
prediction, in-order retirement
Precise Exceptions
Static/Dynamic instruction stream
Active window
Reservation Station (Node table)
Flynn's bottleneck
Latency/Bandwidth issues, on-chip vs off-chip
SIMD
VLIW, Lock-step
Vector processors / array processors, SIMD
Trace Scheduling
Prepare to undo instructions
DEA, Decoupled Execute and Access
Restricted Dataflow
Firing of an operation in dataflow
Trace Cache
storage partitioning
partial matching
inactive issue
branch promotion
trace packing
trace segment collection
HEP
SMT
SSMT