What is register transfer notation? So are you looking for something like:
ADD (opcode 81 /0 id): ADD r/m32, imm32
r/m32 <- r/m32 + imm32Use REG or MEM instead of r/m32. Thus, in this example:
MEM[GPR + DS<<16] <- MEM[GPR + DS<<16] + imm32
GPR <- GPR + imm32
MEM[GPR + disp32 + DS<<16] <- MEM[GPR + disp32 + DS<<16] + imm32
MEM[GPR + SEXT(disp8) + DS<<16] <- MEM[GPR + SEXT(disp8) + DS<<16] + imm32
MEM[disp32 + DS<<16] <- MEM[disp32 + DS<<16] + imm32Do we need to consider prefixes for Homework 2?
No. You do not need to worry about any instruction that has a prefix in its x86 representation.
Do we need to build a decoder or cache for Homework 2?
Not required for Homework 2. Please start from a basic data path. You can add your modules step by step.
Do we need to account for instructions with 8-bit displacements (mode 01)?
Yes, because the operand size is 32 bits (the 8-bit displacement is used for address generation).
Do we need to do JMP rel8 (EB cb) and ADD AL,imm8 (04 ib)?
JMP rel8 uses a 32-bit register, but ADD AL, imm8 uses an 8-bit register, so you need to
implement JMP rel8 but not ALL AL, imm8.
Do we need to do JMP rel16 (E9 cw)?
JMP rel16 requires an operand size override prefix; thus you
do not need to implement it.
Do we have to do the move to and move from segment register
instructions, such as MOV r/m16, Sreg and MOV Sreg, r/m16?
No.
Do we need to do the far jump instructions?
You are required to implement only JMP ptr16:32 for Homework 2. Since
JMP ptr16:16 needs an operand size override prefix, you will implement it
later. You do not need to implement JMP m16:16 and JMP m16:32.
Do we need to do the moves which take moffs?
You do not need to implement those move variations.
Do we need to implement flags ?
Yes.
The base seems to be encoded in mod r/m byte for some addressing modes and in the SIB byte for others. Is this right?
Yes.
If the instruction is OP r32, r32, how do we know which of the registers is represented by the mod r/m bits and which is represented by the middle 3 reg bits?
Chapter two of the second manual discusses this.
The default segment is supposed to be SS if the register used is EBP or ESP. Should we write RTNs keeping this in mind? And does the default segment selection goes as a part of the invisible decode module for this design?
Yes to both questions.
A far jump requires us to change the value in CS register. Does this have to be handled for this assignment?
Yes.