Instructions:
You are encouraged to work on the problem set in groups and turn
in one problem set for the entire group. Remember to put all
your names on the solution sheet. Also, remember to put the name
of the TA and the time for the discussion section you would like the problem
set turned back to you. Show your work.
Please staple your Problem Sets BEFORE coming to class!
  | AND R2, R2, #0 |   R2 <- 0 |
LOOP   | ADD R1, R1, #-3 |   R1 <- R1-3 |
  | BRn END |   End when R1 is negative |
  | ADD R2, R2, #1 |   R2 <- R2+1 |
  | BRnzp LOOP | |
END   | HALT |
For R2 to contain the value 3, the BRn must not have intiated a branch for 3 consecutive times. Therefore, R1 wasn't negative after the instruction ADD R1, R1, #-3 was exectued 3 times and was negative after the instruction was executed 4 times. That is, R1-3x3 = R1-9 >= 0 and R1-3x4 = R1-12 < 0. Solving the inequalities yields, 9 <= R1 < 12. Since a register contains integers, R1 could have been 9, 10, or 11.
  | .ORIG x3000 |
  | AND R4, R4, #0 |
  | AND R3, R3, #0 |
  | LD R0, NUMBERS |
LOOP   | LDR R1, R0, #0 |
  | NOT R2, R1 |
  | BRz DONE |
  | AND R2, R1, #1 |
  | BRz L1 |
  | ADD R4, R4, #1 |
  | BRnzp NEXT |
L1   | ADD R3, R3, #1 |
NEXT   | ADD R0, R0, #1 |
  | BRnzp LOOP |
DONE   | TRAP x25 |
NUMBERS   | .FILL x4000 |
  | .END |
Label | Memory Address |
LOOP | x3003 |
L1 | x300A |
NEXT | x300B |
DONE | x300D |
NUMBERS | x300E |
The instruction AND R2, R1, #1 performs a bit mask (x0001) to decide whether the least significant bit of the value is 0 or 1. The LSB of a number is used to determine whether the integer was even or odd. For example, numbers with a zero LSB are: 0000 (#0), 0010 (#2), 0100 (#4), 0110 (#6), which are all even. Hence, R3 counts the amount of even numbers in the list and R4 counts the amount of odd numbers.
  | ADD R2, R1, #0 |
HERE   | ADD R3, R2, #-1 |
AND R3, R3, R2 | |
BRz END | |
ADD R2, R2, #1 | |
BRnzp HERE | |
END | HALT |
The program finds out the smallest power of 2 which is larger than or equal to the unsigned integer in R1.
.ORIG x3000 | ||
LD R1, FIRST | ||
LD R2, SECOND | ||
AND R0, R0, #0 | ||
LOOP | LDR R3, R1, #0 | ; (a) |
LDR R4, R2, #0 | ||
BRz NEXT | ||
ADD R1, R1, #1 | ||
ADD R2, R2, #1 | ||
NOT R4, R4 | ; (b) | |
ADD R4, R4, #1 | ; (c) | |
ADD R3, R3, R4 | ||
BRz LOOP | ||
AND R5, R5, #0 | ||
BRnzp DONE | ||
NEXT | AND R5, R5, #0 | |
ADD R5, R5, #1 | ||
DONE | TRAP x25 | |
FIRST   | .FILL x4000 | |
SECOND   | .FILL x4100 | |
.END |
.ORIG x3000 | ||
AND R0, R0, #0 | ||
LD R1, NUMBITS | ||
LDI R2, VECTOR | ||
ADD R3, R0, #1 | ||
CHECK   | AND R4, R2, R3 | |
BRz NOTOPER | ||
ADD R0, R0, #1 | ||
NOTOPER   | ADD R3, R3, R3 | |
ADD R1, R1, #-1 | ||
BRp CHECK | ||
LD R2, VECTOR |   <- missing instruction | |
STR R0, R2, #1 | ||
TRAP x25 | ||
NUMBITS   | .FILL #16 | |
VECTOR   | .FILL x3500 | |
.END |
R2 contains the bit vector, and not the address at which the bit vector is contained. The instruction LDI R2, VECTOR loaded the value at x3500 into R2 since the value at the memory address labeled as VECTOR was used as the address from which to load. The store instruction STR R0, R2, #1 uses the value of R2 to evaluate an address. However, R2 must be modified to contain an address for an STR instruction to work. Thus, LD R2, VECTOR is an additional required instruction.
.ORIG x3000
LD R0, Addr1
LEA R1, Addr1
LDI R2, Addr1
LDR R3, R0, #-6
LDR R4, R1, #0
ADD R1, R1, #3
ST R2, #5
STR R1, R0, #3
STI R4, Addr4
HALT
Addr1 .FILL x300B
Addr2 .FILL x000A
Addr3 .BLKW 1
Addr4 .FILL x300D
Addr5 .FILL x300C
.END
Without using the simulator, answer the following questions:
What will the values of registers R0
through R4
be after the LC-3 finishes executing the ADD
instruction?
R0 - x300B
R1 - x300D
R2 - x000A
R3 - x1263
R4 - x300B
What will the values of memory locations Addr1
through Addr5
be after the LC-3 finishes executing the HALT
instruction?
Addr1 - x300B
Addr2 - x000A
Addr3 - x000A
Addr4 - x300B
Addr5 - x300D
Bob Computer just bought a fancy new graphics display
for his LC-3. In order to test out how fast it is, he rewrote the OUT
trap
handler so it would not check the DSR
before outputting. Sadly he discovered
that his display was not fast enough to keep up with the speed at which the LC-3
was writing to the DDR
. How was he able to tell?
Some of the characters written to the DDR weren't being output to the screen.
Bob also rewrote the handler for GETC
, but when he typed
ABCD
into the keyboard, the following values were input:
AAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBCCCCCCCCCCCCCCCCCCCDDDDDDDDDDDDDDDDDDDD
What did Bob do wrong?
The handler didn't check the KBSR before inputting the character.
15 | 0 | |||||||||||||||
x3000 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
x3001 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
x3002 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
x3003 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
x3004 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
x3005 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
x3006 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Jane Computer (Bob's adoring wife), not to be outdone
by her husband, decided to rewrite the TRAP x22
handler at a different place in
memory. Consider her implementation below. If a user writes a program that uses this
TRAP
handler to output an array of characters, how many times is the ADD
instruction at the location with label A
executed?
Assume that the user only calls this "new" TRAP x22
once. What is wrong with this TRAP
handler?
Now add the necessary instructions so the TRAP
handler executes properly.
Hint: RET
uses R7
as linkage back to the caller.
; TRAP handler
; Outputs ASCII characters stored in consecutive memory locations.
; R0 points to the first ASCII character before the new TRAP x22 is called.
; The null character (x00) provides a sentinel that terminates the output sequence.
.ORIG x020F
START ST R7,SAVER7
ST R1,SAVER1
LDR R1, R0, #0
BRz DONE
ST R0, SAVER0
ADD R0, R1, #0
TRAP x21
LD R0, SAVER0
A ADD R0, R0, #1
BRnzp START
DONE LD R7,SAVER7
LD R1,SAVER1
RET
SAVER0 .BLKW #1
SAVER7 .BLKW #1
SAVER1 .BLKW #1
.END
How many TRAP
service routines can be implemented in the LC-3? Why?
Why must a RET
instruction be used to return from a TRAP
routine? Why won't
a BRnzp
(unconditional BR
) instruction work instead?
How many accesses to memory are made during the processing of a TRAP
instruction?