levels of transformation
algorithm
problem
electronic devices
transistor
natural language
instruction
machine state
voltage potential
language
high level language
low level language
Instruction Set Architecture (ISA)
Microarchitecture
circuits
electrons
assembly language
compiler
assembler
interpreter
tradeoffs
cost vs. benefit
opcode
operands
memory
address space
binary
unary
bit
codes
ASCII
address space
integer
2's complement
floating point
data types
look up table
ALU
unsigned
overflow
sign bit
data path
positional notation
fixed point
byte
most significant bit (MSB)
least significant bit (LSB)
sign extension (SEXT)
zero extension (ZEXT)
significant digits
signed magnitude
exponent
fraction
precision
normalized form
excess code (bias)
binary point
binary string
Hexadecimal
Logical Operations
Bitwise Operator
Logical Value
Binary Operator
Operand
Function
Associative
Truth Table
Equivalent Function
AND
OR
NOT
Exclusive OR
Complementary
Inverting Function
Gate
N-type
P-type
CMOS
Inverter
mask
transmission voltage
memory
address
decoders
MUX
ALU
(clock) cycle
clock
storage structure
processing
decision structure
combinational logic
sequential logic
carry
sum
carry-ripple
PLAs
gates
NAND
NOR
full adder
logically complete
De Morgan's Law
"Don't Care"
Signal
DRAM
Capacitor
Volatile Memory 
Non-volatile Memory
Latch
Gated Latch
Set/Reset Lines
Propagation Delay
Quiescent State
Memory
Memory Address Register (MAR)
Memory Data Register (MDR)
Load
Store
Write Enable
Field
Decision Structure
Storage Structure
Address Space
Adressability 
State
Finite State Machine
Cycle Time
State Diagram
Sequential Circuit
Combinational Circuit
Finite State Machine
Control
Clock
D-Latch
Master
Slave
Memory
Input Device
Processing Unit
Temporary Storage
Registers
Program Counter
Instruction
Instruction Register
Fetch Phase
Load
Store
Decode
Opcode
operands
Source