Instruction
registers
operands
load/store machine
literal/immediate data
steering bit
operate instructions
data movement instructions
control instructions
Bus
trap vector
condition codes
Indirect/pointer
oscillator 
opcode
source register
destination register
3-address
PC
MAR
IR
Register file
operating system
sequential
iterative
conditional
condition codes
trap
branch
load
store
load indirect
tri-state
gating the bus
structural programming
Stepwise refinement
Systematic Decomposition
Control characters
Initialization
Linker
Executable image
Pointer
assembler
label
Reserved
run time error
assemble time error
.orig
.end
.fill
.blkw
linker
pseudo-op
two pass
symbol table
assembly time error
offset
memory-mapped IO
keyboard status register (KBSR)
keyboard data register (KBDR)
ready bit
polling
display data register (DDR)
display status register (DSR)
address control logic
interrupt
interrupt enable bit
I/O instruction
direct memory access (DMA)
spin
interrupt driven I/O
Callee
Caller
Boot
Trap Routine
JMP
trap vector table
trap instruction
return address
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