Tue, 12 Nov 2013, 00:35

My students,

Two of my TAs mentioned this evening that MIO.EN and MEM.EN are still
confusing to some of you.  So, this email is to try one more time to 
make it clear.

If you look at the address control logic, you will see that MAR is an
input to that logic.  Since there is always something in MAR, the output
signals (whether to store to memory or to one of the three I/O device
registers that one can write to, and whether to read from memory or to 
one of the three I/O device registers that one can read from) "could" 
always be asserted.  

[Asserted means = 1, i.e., "do it!"].  But just because the MAR has an
address in it does not mean we want to read or write from memory or I/O 
right now.  We only want to read or write from memory or I/O in a 
*particular* cycle.

I gave you the example in class.  If I do a Store instruction, do I put
data into MDR before or after I put an address into MAR?  Suppose I put
the address into MAR first.  Do I want to store as soon as that address
specifies memory or I/O device register?  Of course not!  I want to wait
until after I have MDR and MAR properly loaded and then I want to do the
store to either memory or I/O device register.

The MIO.EN solves this problem.  It is an input to the Address Control 
Logic.  It is the "do it now!" signal.  That is, if MIO.EN is 0, then 
even though MAR specifies an address in memory or a device register, 
nothing happens.  All the outputs of the address control logic are 0 
(that is, NOT asserted).  It is only in the cycle when MIO.EN is asserted 
(= 1) that the memory or I/O device register activity actually happens.

Summary: MIO.EN = 1 -> do the memory access or device register access in
this cycle.

What about MEM.EN?  Again look at the Address Control Logic.  What is the input
to this logic?  Answer: MAR, MIO.EN, and R/W.  What is the output?  Answer:
MEM.EN, LD.DSR, LD.DDR, LD. KBSR (for output) and two control signals to
identify the source (memory, DSR, KBSR, KBDR) of a read.  That is, if the
MAR identifies a memory location, MEM.EN is the signal to read or write to
memory.  That is, MEM.EN =1 -> we are reading or writing to memory.  If MAR
identifies a device register address, MEM.EN =0, memory is not accessed, but
instead one of the device registers is either written to or read.

A simple truth table might help:

MIO.EN  MEM.EN  |  what to do
-|-
   0      0     |  MIO.EN = 0 -> do nothing this cycle.
   0      1     |  never happens since MIO.EN has to be 1 for MEM.EN to be 1.
   1      0     |  Do something with one of the device registers this cycle.
   1      1     |  Do a read or write of memory this cycle depending on R/W.

OKAY?

Good luck with the exam on Wednesday.

Yale Patt