Are we changing the datapath/state diagram to detect or generate the interrupt or exception?
As part of this lab, you are changing the datapath and state diagram to detect both the protection exception and the timer interrupt. However, you are only simulating the generation of the timer interrupt.
Should INTV/EXCV be left-shifted by 1 before adding to the interrupt/exception vector base register?
Yes. INTV/EXCV is an index into the interrupt/exception vector table and as each entry stores an address, INTV/EXCV has to be left-shifted by one to get the correct offset in this table.
You should generate the timer interrupt only once – at cycle 300. You must also take care of setting the global variable INTV to the correct interrupt vector at this time.
What kind of file format should we write for the readme file?
Please submit a hard copy of your report in class.
You need to change in the shell code which we provided to you the
enum CS_BITS and the struct System_Latches.
Your simulator should generate the timer interrupt once at cycle 300. You
can implement this by using the CYCLE_COUNT variable we provided.
What should PSR[15] be initialized to?
You should initialize the privilege mode of the processor (PSR[15]) to 1 (user mode) in your simulator.
Can a user program execute the RTI instruction?
You can assume that RTI will never be used by a user program. You are not responsible for generating an exception if an RTI instruction is encountered in user mode.
Who initializes the user stack pointer?
The user stack pointer is initialized in the user program (if the user program makes use of the stack). The supervisor stack pointer is initialized by the shell code we already provided.
Can we assume that we do not get interrupts/exceptions when the processor is in system (supervisor) mode?
For the purposes of this assignment, you can assume this.
What is the size of the data elements our user program is supposed to add?
The elements your user program is supposed to add are bytes. You should store the sum of
the 20 8-bit two's complement integers as a 16-bit word at location xC014.
Can I execute one cycle of the memory access (for example in state 33) before handling the exception?
No. You should not access memory if the access causes an exception.
You may declare registers you need as part of the System_Latches struct.
TRAP should be able to execute in user mode, i.e. it must be able to access the trap vector table at x0000 to x01FF without causing a protection exception.
You may add a line to the initialize() function in the shell code to set the initial value of the PSR.
Please note that LEA no longer sets condition codes.