Project Description

Design Reviews

We will hold at least two design reviews for each team this term. More will be held if necessary. Both will be in ENS 537, and will be conducted by the TAs and Prof. Patt (Sometimes one of our Ph.D. students will wander in to learn some new ideas and ask questions. If he keeps asking questions, you should feel flattered that what you have said has impressed him). All members of the design team must be present for each review. The purpose of a design review is to verify the integrity of the design and to catch problems before they become major. We will review your design decisions, performance/cost considerations, and other tradeoffs involved in your design. We will attempt to insure that, in fact, the machine, if built, will perform as specified. The first design review is largely for your benefit. The more you can get from it, the easier the final stages of your project will be. As mentioned in problem set 5, you should bring 4 copies of all relevant schematics/block diagrams.

Final Design Review

At the final design review, you will be expected to turn in a complete design of that portion of an x86 implementation described below. This is to include state diagrams, data path, complete circuit drawings, parts list, and a complete description of the control logic.

As part of the final design review, we will provide you with several test programs to evaluate the correctness and performance of your design. We will expect you to demonstrate via the structural level Verilog simulation of your design that your design can execute the test programs. Sample test programs will be available a week before the final design review for your use in preparing for this.

Your design is to include at least the following:

1. All opcodes and prefixes covered in the problem sets.
2. All addressing modes and data types covered in the problem sets.
3. Instruction and data caches.
4. The design and specification of the external bus.
5. The handling of cache accesses and memory, including the functionality of an MMU and basic segmentation.
6. The design of one simple and one complicated I/O device.
7. The handling of exceptions (e.g., segment limit) and interrupts (e.g., I/O device).
8. A responsible cycle time. Particularly careful attention to cycle time will not go unnoticed in the grading.

Optionally, you may wish to include other features, as your creativity suggests, and time permits.

If you feel that you cannot complete the above before the end of the semester, you are strongly encouraged to talk to the instructor and TAs about it.

The Final Report

Subsequent to the design review, but not later than the date scheduled for the final exam, you are expected to turn in a final report describing your design. The report is to be written in clear, understandable English. The information must be clear and legible, accompanied by well laid out diagrams, as appropriate. We must stress that it is your responsibility to convey the information contained in your design. For your convenience, the following items should be used as a checklist of what we would expect to be included in an acceptable report:

1. Title Page, Abstract, Contents, Chapters, Appendix.
2. Introduction: General requirements, features, design approach.
3. Design discussion: Brief description of control and data path, both high-level and low-level.
4. Design considerations: Description of goals and priorities. Discussion of the tradeoffs you considered in determining your implementation.
5. Critical path analysis, including relevant timing diagrams.
6. Final design decisions relating to the items of part (4).
7. Conclusions: Discussion of constraints, performance, cost, recommendations for a next design, etc.
8. Appendixes:
   1. Microinstruction format, and microcode listings, where and if appropriate.
   2. Schematics, as appropriate.

A Final Note: Neatness, spelling, English usage, clarity, and organization of the material cannot be emphasized too much.