The next step in your computer design is to add the control. This is the last assignment that you will work on by yourself. Starting with problem set 5, you will be part of a group, and we will expect to see a single solution from the entire group.
In this assignment, you are asked to specify the mechanism for generating the control signals that control the data path. This means all the control signals that will be needed every cycle to process every opcode, data type, and addressing mode that has been specified thus far. If you are planning to use microprogrammed control, these control signals will be generated centrally. Your job in this assignment is to specify the microinstruction, its fields for controlling the data path and the microsequencer, and the micro-orders that make up each field. If you are planning to pipeline your design (highly recommended), then these control signals will be distributed over the various stages of the pipeline for processing each ISA instruction through the entire pipeline. Where each control signal for each stage is generated is your decision. Also, for a pipelined design, it is important to provide sufficient interlocks to ensure safe execution of each instruction through the pipeline.
Your specification at this point does not have to specify the actual logic required to generate each control signal. However, we do want to see input/output behavior; that is, we want to see what input signals are required to specify each control signal. These can be shown as block diagrams on your drawings.
Submit a document which lists each control signal, describes how it is generated (i.e., input/output behavior), and which stage it is used in (if your design is pipelined).
Specify all the control logic required to completely emulate one of the three sets of x86 instructions specified below. Complete emulation means all stages after decode. Use Verilog to implement your design. Fetch and Decode stages can be implemented with simple behavioral constructs.
Please use structural Verilog to implement logic structures for your chosen test case. For example, if you are doing the register file test case, please implement the register file in structural Verilog. You can implement the other structures (such as caches and dependency checker) in behavioral Verilog in this case. However, note that you should still design and show all of the structures the homework description requires in your data path and control path.
Simulate your design and verify that it works for the set of x86 instructions you have chosen. Use DVE to monitor important data and control signals in the cpu. Submit annotated hard copies of your DVE waveforms. Please make sure that all signals on the printouts are readable and consistent with part 1. Use several pages if necessary.
Submit a block diagram of your datapath with explanations to clarify all signals shown.
Assume that testcase starts at memory location x3000.
MOV EAX,0x12340000 // B8 00 00 34 12
MOV ECX,0x00001234 // B9 34 12 00 00
ADD EAX,ECX // 01 C8
ADD EAX,#-1 // 83 C0 FF
HLT // F4 MOV EAX, 0x12341234 // B8 34 12 34 12
JMP Down // E9 05 00 00 00
MOV EAX, 0xFADEDACE // B8 CE DA DE FA
Down ADD EAX, #1 // 05 01 00 00 00
HALT // F4 MOV EAX, 0xCAFEFFFFF // B8 FF FF FE CA
MOV CL,0X01 // B1 01
MOV DL,0X02 // B2 02
ADD AX, 01 // 66 05 01 00
MOV CH, CL // 88 CD
HLT // F4