Fri, 14 October 2016, 23:27

A student writes:


> Hello Dr.Patt,
>
> For JMP instruction (i.e PC <- BaseR) there are 2 possible combinations for
> control store
>
> 1.
> BUS <- BaseR (Through ALU Pass A)
> PC <- BUS (By setting PC_MUX=01)
>
> 2.
> PC = Output of adder (PC_MUX=02)
> and the input of the adder are
> (a) 0 (coming from the ADDR2MUX)
> (b) SR1 (coming from the ADDR1MUX)
>
> Basically in 1, PC is loaded from the bus and in 2 in loaded from the
> internal data path. I believe both of them to be correct. Can we implement
> either for lab3? If you take rdump after JMP operation, the BUS value may
> not be as expected, so I wanted to check
>
> Thanks in advance,
> <<name withheld to protect the student who sees more than one solution>>


Good observation.  The microarchitecture has a lot of data path so it should
not surprise one to discover that there are cases where there is more than one
way to do the job.  ...any more than it should surprise one to discover that
there is more than one way to fly from Austin to San Francisco.  One can fly
to Dallas, and then on to San Fracisco.  Or to LAX and then on to SFO.  or to
Houston, and then on to SFO.

Which way you fly or which data path you use in such cases is completely
up to you.

Good luck getting the lab done this weekend.


Yale Patt