The complex I/O device required for the project is a disk which includes a Direct Memory Access (DMA) controller. The DMA controller is responsible for the communication between the memory and the disk.
The only operation required for this project is to transfer data from the disk to the memory. Transfer in the opposite direction (memory to disk), while equally important, will not be required in the interest of cutting down on your workload.
Communication between the CPU and the DMA controller, and between Memory and the DMA controller is done via the bus.
To start a DMA operation, the CPU first writes to four registers
(memory mapped and chosen by you) in the DMA controller. They are:
1) The source address on the Disk (32 bit address that represents the
"cylinder/sector/block" of the Disk).
2) Destination address (32 bit physical memory address)
3) Size (the number of bytes being transfered). A DMA transfer can be
anywhere from a single byte to a maximum of 4KB.
4) A single bit register that is written by the cpu to tell the DMA
controller to initiate the transfer.
The DMA controller transfers the data from the disk to a buffer in the DMA controller. You can implement the disk and the buffer in behavioral verilog. We will assume infinite bandwidth between the disk and the buffer, and a fixed latency of 750ns for the transfer to complete, independent of the size of the transfer.
After the DMA controller has all the data requested, it will request the bus to forward it to physical memory. You can assume a transfer will never cross a page boundary.
Note: there are 32 data lines on the bus. After the transfer has completed, the DMA controller will notify the cpu via an interrupt. The intent is to have the transfer take place in parallel with other CPU instructions. Note further that the CPU can use the bus or memory for other instructions and should not stall because of the DMA operation.