Mon, 30 Sept 2019, 01:42 gated latches vs master-slave flipflops

My students,

As you know, there will be no lecture tomorrow (Monday), and instead I want you
all to take stock of what you know and what is unclear, and do not hesitate to
use our class time tomorrow to push the TAs to explain concepts you are still
having trouble with.

I have been told over the years that one of the concepts that takes a while 
to understand is the reason for master-slave flipflops; that is, why gated 
latches will not do the job of being able to read and write a bit in the same 
cycle.  I have overhauled my explanation of this in the 3rd edition of the
book.  I hope it makes sense to you.  In case it still doesn't, I am writing
a few words here to hopefully help you understand.  Please do question my TAs 
if it is still not clear.

1. The key idea behind the gated latch is that as soon as you write a 1 or 0
into it, it is available at the output, and can affect subsequent behavior.
Let's see why.

2. Let's look at an example from our discussion of the computer's state machine
on Wednesday. Each instruction is processed by the computer going through its
instruction cycle.  The first phase FETCH is to get the instruction from 
memory and put it in the instruction register (IR).  In the very first clock
cycle, we load the MAR with the contents of the PC and we load the PC with the
contents of the PC + 1.  We load the MAR with the contents of the PC because 
the PC contains the address of the location in memory of the instruction we 
wish to FETCH.  We load PC with the contents of PC after adding 1 to it, so at 
the start of the next instruction cycle, the PC will contain the address of 
the next instruction in memory to be fetched and processed.

If we used gated latches for the PC, we would have the situation where we are
adding 1 to the PC, giving PC+1, which would immediately add 1, giving us 
PC+2, which would immediately...  So, as long as the gate signal to the gated
latch is 1, we could continue to cycle, continually adding 1 to the PC.  At the
end of the clock cycle, rather than have the value PC+1, we would have PC +
however many round trips the circuits could make, adding 1 each time.  We do
not want that; ergo, the gated latch won't work!

3. What if we use a master-slave flipflop.  The state of the flipflop is the
output of the slave gated latch.  It remains fixed for the duration of the
clock cycle, in this case containing the contents of the PC.  During the clock 
cycle, the logic specifies PC+1, and that value gets written into the master 
gated latch, but does not affect the slave gated latch until the start of the 
NEXT clock cycle when the slave latch is set to the value that was determined 
in the previous cycle and was set in the master gated latch.  In this way, 
whatever is in the slave latch can be read throughout the clock cycle, but 
only takes on its newly computed value (in this case PC+1) at the end of the 
clock cycle, which is also the start of the next clock cycle.

4. Bottom line: if you want to be able to read and write a value in the same
clock cycle, you need a flipflop; a latch can't do the job.  If the value 
consists of n bits, then we need n flipflops, and we call the structure a
n-bit REGISTER.

I hope the above helps.  If things are still muddy, please ask one of the TAs.
In fact, perhaps first see if one of the members of your study group can 
explain it to you.  If not, then one of the TAs, and if that doesn't work,
please see me.  

See you on Wednesday.


Yale Patt