Date: Sat, 6 Apr 2019 01:47:47 -0500
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From: "Yale N. Patt" <patt@ece.utexas.edu>
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To: a.deshmukh@utexas.edu, mohammadbehnia@utexas.edu, chestercai@utexas.edu
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Subject: Lab 4 problem
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Message-ID: <20190406064747.GD28848@ece.utexas.edu>
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My students, my answer to this student's question is longer than usual,
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so if you are having no trouble understanding what is expected, feel free
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to delete and move on. 
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A student writes, (a) because he has technical questions about Lab 4, and
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(b) because he wants more time to do the lab, even though he really does 
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not have a great excuse.
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> Dear Dr. Patt,
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> 
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> Looking at the lab 4 document, I noticed the first question on the FAQs
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> says that we only need to simulate the generation of the timer interrupt.
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> 
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> "1. Are we changing the datapath/state diagram to detect or generate the
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> interrupt or exception?
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> 
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> As part of this lab, you are changing the datapath and state diagram to
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> detect both the protection exception and the timer interrupt. However, you
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> are only simulating the generation of the timer interrupt."
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I guess we need to look carefully at what your task is on lab 4.  You have the 
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results of lab 3, where you had to add control signals to process each of
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the LC-3 instructions.  What instruction you process at any point in time
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depends on where you are in executing your program.
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In this lab you need to add whatever it will take to process (i.e., handle) 
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the timer interrupt and the three exceptions (i.e., unaligned access, unused 
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opcode, and protection). That means adding more states, data path and 
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microsequencer structure to be able to detect and handle each of these four
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different events when they show up.
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In the case of exceptions, you do not need to add anything to your Simulator
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to make them show up.  They will show up as a result of problems in a program.
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Your job: Detect them with your additional microarchitecture states if they 
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show up.  The timer interrupt should also show up at its expected time interval.
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However, the timer interrupt is part of the hardware.  That is, the program 
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will not cause the timer interrupt to happen.  We need something to cause the 
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timer interrupt to happen at 300 cycles so the lab 4 additions to your 
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microarchitecture can handle it.  A piece of code that you will write to 
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simulate the timer interrupt will do.  
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> Does this mean we would need to include microarchitecture support for the
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> generation of the timer interrupt or only for its detection? 
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Only for its detection and processing.  We are adding the following 
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paragraph to the lab description. Perhaps you will find it useful:
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Micro-architecture support needs to be added only for detecting interrupts, 
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not generating them.  You can generate the interrupt as follows: Since you 
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are simulating an interrupt at cycle 300, you can have an if() statement in 
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the cycle() function that sets the interrupt vector (INTV) to the appropriate 
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value at cycle 300 using the CYCLE_COUNT variable. Recall that unlike 
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exceptions, you can check for interrupts and deal with them whenever it is
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convenient for you to do so.  That is, you do not have to deal with the
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interrupt immediately, you may choose to deal with the interrupt whenever
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it is convenient for you
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> In other
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> words, I implemented the timer interrupt in the form of a current register
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> that's decremented each cycle. Would I need to include support for loading
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> and decrementing this current register in the datapath or simply for
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> checking if the current register is zero to trigger the interrupt?
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>
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> Also do we only need to detect the protection exception and timer interrupt
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> in the microarchitecture, or should we detect the other exceptions as well?
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As I said above, you need to augment the microarchitecture so it can detect 
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and process three exceptions.
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> I also would like to ask you to extend the lab 4 deadline if possible. This
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> past week has been very busy for me, and I haven't been able to get as much
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> work done on this lab as I had planned.
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Not really the greatest excuse in the world.  But I do think lab 4 is the 
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most demanding lab, so I will give you two more days to do it.  New due date, 
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Next Tuesday night at 11:59pm.  I hope that extra time results in a lot of 
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high grades.  It is going to cost you two days in the time available for lab 5.
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> Thank you,
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> <name witheld to protect a student who has been too busy to do lab 4 in time>>
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You are welcome.  Good luck finishing this lab by Tuesday night.
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Yale Patt
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