Sun, 11 Oct 2020, 16:01

A student writes:
> Hi Dr. Patt, I hope you are doing well.
>
> As I was finishing up Lab 3, I had a question about the DATA.SIZE signal
> for the data path. I understand that DATA.SIZE is being used when the MDR
> is gated on to the bus in order to determine whether to put the entire word
> or just the low/high (depending on MAR[0]) sign extended byte on to the
> bus. However, I couldn't figure out why the signal is being used when the
> MDR is loaded with something from the bus. My understanding is that if
> MAR[0] is a 0 then the MDR will be loaded with the entire 16 bits from the
> bus but if MAR[0] is a 1 then the MDR[15:8] and MDR[7:0] will both be
> BUS[7:0]. This is what I am using for my logic in PL3 (and it seems to work
> for my test cases), so my question is: why is the DATA.SIZE signal
> necessary for this case and does it need to be part of the ucode file for
> the states where the MDR is being loaded with a value from the bus?
>
> Thanks,
> <<name withheld to protect the student who is absolutely correct>>

Thank you for the question.  I am sending it to the whole class because it is
important that everyone sees it.  You are absolutely correct. 

The MDR is loaded from the bus in preparation for storing a byte or word
to memory. 

If MAR[0] is a 0, then BUS[15:0] is loaded into MDR.  If we wish to write a
word into memory, that is accomplished by asserting both WE1 and WE0 during
the state when we do the write.  If we wish to write a byte then WE1 is not
asserted.

If MAR[0] is a 1, then BUS[7:0]'BUS[7:0] is loaded into MDR.  (That is, both
high and low bytes of the MDR are loaded with BUS[7:0].)  During the state in
which we actually store the byte, WE1 is asserted, but WE0 is not asserted.

The DATA_SIZE control signal is superfluous, completely unnecessary with
respect to the logic that outputs the left input to the MIO.EN MUX.

Thanks for bringing it to my attention.  We should replace that logic block
with a 2-input MUX, controlled by MAR[0].  The two inputs are BUS[15:0] and
BUS[7:0]'BUS[7:0}.

Good luck finishing Lab 3 on time.

YNP