Sat, 17 Oct 2020, 23:37

A student writes:
> Hello Dr. Patt,
>
> The logic block below the MDR register has inputs DATA.SIZE and MAR[0]. In
> appendix C at C.5.2, the document says MDR is loaded with SR[15:0] if
> MAR[0] = 0, and SR[7:0]'SR[7:0] if MAR[0] = 1. I understand this is to
> align the data for a byte store. However, later in the same section, the
> document says that the MDR is loaded with SR[7:0]'SR[7:0] if DATA.SIZE =
> BYTE, but doesn't mention MAR[0]. So, if DATA.SIZE = BYTE and MAR[0] = 0,
> would SR[15:0] be loaded into the MDR or is SR[7:0]'SR[7:0]? Which one is
> correct?
>
> Regards,
> <<name withheld to protect the student who found my inconsistency>>

First, thank you for pointing out the inconsistency.  Both ways will work,
and I should have stuck with one way, in this case the first discussion,
which is consistent with my answer to the student last weekend.  BYTE_SIZE
is not needed.  MAR[0] alone will do the job. 

With respect to using BYTE_SIZE, rather than MAR[0], that will also work with
respect to loading MDR.  If the STB instruction is being processed, MAR[0] is
not needed in the clock cycle that MDR is loaded.  We simply load bits[7:0]
into both halves of the MDR.  In the state when the actual store is done,
MAR[0] will enable the correct byte write enable signal, so the correct byte
of memory will receive bits[7:0] of the data to be stored.

I apologize for adding unnecessary confusion by describing both ways.  In
hindsight, I should have stuck with one.

Good luck getting the lab done by midnight tomorrow.  I will see you in class
on Monday.

Yale Patt