Fri, 06 Nov 2020, 14:57

A student writes:
> Dear Professor Patt,
> Hi,
>
> Appendix A.4 says:
>   In order for an interrupt to occur, the following must be true:
>     1. The Interrupt Enable bit (IE) associated with the event must be set
> (i.e., IE=1).
>     2. The *priority of the event must* be greater than the *priority of
> the process* that is executing.
>
> However, Appendix A.1 does not mention a priority level in the PSR.
>
> For lab 4, do we ignore the timer interrupt priority, and assume that the
> timer interrupt is always more important than the user program?
> Or should we add priority bits to the PSR? If so, what should the priority
> of the timer interrupt be?
>
> Thank you,
>
> <<name withheld to protect the student who has pointed out a glaring omission>>

Thank you for the question.  Somehow my intent on what I wanted in Appendix A
got lost, so I will explain it here.

First I apologize for the omission.  In fact, my TAs have simplified the lab
in order for you to do it without the specific information you are asking for.
Given the fact that it is now Friday and most of you are well on your way to
completing the lab, it is important that I do nothing to derail the work you
have already done.  I am very cognizant of that.

So, I begin:  The lab, as represented by the information you have says nothing
about the priority of the timer interrupt.  BAD.  Every interrupt MUST have a
priority associated with it.  For purposes of this lab ONLY, you can simply
assume that all user code is executing at priority 0, and the timer interrupt
is coming in at a priority greater than 0.  Given that I let you assume that,
you do not have to check the priority of the timer interrupt against the
priority of the running process.  When the timer interrupt signal is asserted,
you can assume it is of a higher priority and initiate the interrupt.

The above paragraph is my way of making sure  that those who have assumed that
do not incur extra work to do now.

Still I would be remiss in not fixing the problem for future students in 460N.
So, next time I teach 460N, Lab 4 will be updated as follows.

1. The PSR.  The PSR has three relevant fields:

PSR[15]: the privilege level of the process running.  0 = kernel, 1 = user.
PSR[10:8]: the priority level of the process running.
PSR[2:0]: condition codes (N,Z,P)

2. Priorities:
Timer interrupt: Priority = 5 (101)
user code: priority = 0 (000).
Keyboard interrupt (remember EE306, lab 5): Priority = 4 (100)
Power fail: priority = 6 (110)
Machine check: Priority = 7 (111)

3. Students will have to add data path structures to compare the priority
of the running process with the priorities of any interrupts that want service
and either ignore or take the interrupt depending on which is higher.

I hope the above helps.  Again I apologize that it was not in the documentation.
It will be for next semester.  And, I want to be sure its absence does not
adversely affect your work on the lab.

Any further questions on this, please do not hesitate to let me know.

Good luck finishing the lab by Sunday night.
...and most importantly, stay safe.

Yale Patt