On Wed, Apr 1, 2020 at 4:27 AM Yale N. Patt <patt@ece.utexas.edu> wrote:

A student writes:

> Hello Dr. Patt
>
> Need help in understanding a few concepts :
>
>
>  1. What is the difference between Enlarged basic blocks used in Block
>  structured ISA and Superblocks? (looks like one is SESE while other is
>  SEME).

I do not recognize SESE and SEME. As to Enlarged basic blocks vs Superblocks,
they both consist of instructions, but there the similarity ends. Recognizing
the benefits of the basic block as the atomic unit of processing (i.e., either
all instructions commit or none do), we combine a basic block (call it B) with
one of the two basic blocks (C or D) that are the targets of the conditional
branch that terminates block B. That is, our enlarged block is formed from
B and C or from B and D. The result is a larger atomic unit of processing
that has the same atomic unit characteristic (i.e., either all or none change
architectural state).

A superblock consisting of basic blocks (B and C) or (B and D) simply chooses
whichever of C or D is the more common result of the branch instruction that
terminates block B, and places it in contiguous memory immediately following
block B. Each instruction in the superblock retains its atomic unit
characteristic. That is, each instruction changes the state of the machine
when it retires. The benefit of the Superblock is that since the resulting
fall through path is the common case, instruction fetches can much more easily
fetch beyond the branch instruction terminating block B.

>  2. Is it correct to say that Hyperblocks are enlarged blocks with
>  predicate?

No, Hyperblocks are Superblocks that are made larger by not terminating on a
branch that can be predicated, thereby enlarging the size of the Superblock.

>  3. Why soft errors have become relevant due to frequency.? (Flipping of
>  value by Alpha particles could cause any circuit to malfunction
>  irrespective of the frequency.)

I am told that the problem does not occur at lower frequency. 

>  4. Fast Track vs Slow track. -> In this we mentioned multiple flavors of
>  ISA. So does it mean that there is a difference in the semantic gap
>  between Fast ISA vs slow ISA? Or if we have different hardware
>  implementation then why it is part of compile-time mechanisms.

I prefer to think of it as multiple subsets of an ISA. That is to say, if
we have some instrutions in the ISA that cause the microarchitecture to
perform more slowly or require too much energy, one could (my suggestion)
tell the compiler that if you do not use the full ISA in generating your
object modules, in particuler do not implement instructions A, B, and C,
you will be able to run it on our chip much faster since we will implement
a microarchitecture that ignores A,B, and C, and by so doing, can execute
programs much faster. Why? Because instructions A, B, and C create
bottlenecks that can be ignored if those instructions are not implemented.

In my view, you could end up with a chip with several perhaps domain-specific
microarchitectures, each good for its subset of the ISA, and each running very
fast, and one 486-equivalent perhaps that runs comparatively slow but
implements the entire x86 ISA. The 486-equivalent is the slow track, each of
the other microarchitectures are the fast track.

> Regards
> << Name withheld to protect the student who needs help with a few concepts>>

Hope the above is helpful. Good luck on the exam.

Yale Patt