Thurs, 21 Sept 2023, 15:57 An error in the textbook

My students,

There is an error on page 156 in the textbook.  The last sentence at the bottom of the page gives the 
strong impression that store instructions set condition codes.  That is NOT the case as I have said many 
times already in class.  ONLY six instructions set condition codes: ADD, AND, NOT, LD, LDR, and LDI.  In 
fact, in class we showed that the value loaded into one of the eight general purpose registers is obtained 
from the bus.
In the case of ADD, AND, and NOT, the output of the ALU is put on the bus and then loaded into one of 
R0, ...R7.  In the case of LD, LDR, and LDI, the value in MDR is put on the bus and then loaded into one of 
R0,...R7.
In all six cases, since the value is on the bus it is also input to the logic that sets N, Z, or P.

The last six lines of page 156 should say:  

If the instruction is a load (0010, 0110, or 1010), the computed address
(PC+offset9 in the case of 0010) specifies the memory location to be accessed.  Its contents is loaded 
into the register specified by bits [11:9] of the instruction, and the N, Z, P one-bit condition codes are 
set, depending on whether the value loaded is negative, zero, or positive.  If the instruction is a store 
(0011, 0111, 1011), the contents of the register specified by bits [11:9] of the instruction is written into 
the memory location specified by the corresponding addressing mode of the store instruction.  In this 
case, the one-bit condition codes (N,Z,P) are not changed.

Yale Patt