These are the buzzwords for this semester. See the Glossary of Buzzwords from Fall 2005 to Present for explanations of each buzzword.

List of Buzzwords:
Static Random Access Memory (SRAM)
NVM (nonvolatile memory)
Dynamic RAM (DRAM)
ROM
Persistent vs volatile memory
Memory capacity/density, latency, reliability
Latches/registers
Word line
Bit line
6T SRAM Cell
1T1C Dram Cell
Hard disk: head
Physical address
Chip enable
Write enable
Chip address
Unaligned access
Address/data bus
Interleaving
Row address
Column address
Row address strobe
Column address strobe
Row buffer
Page mode
Row buffer hits
Row conflict
DRAM banks
Reorder buffer
Program order
Retire/Commit
Heterogeneous Element Processor (HEP)
Multithreading
Process
The process state
Thumb and T bit
Virtual memory
Virtual/physical address
Context switch
Task State Segment
Hardware process control block
Priority level
Privilege level
Condition Codes
Compatibility bit
VAX virtual memory
X86 auxiliary flag
BCD arithmetic
Machine check
Interrupts
Exceptions
Fault vs. trap
Interrupt latency
Commercial instructions
IT block
Address translation
Thrashing
Balance set
Working set
Virtual memory translation
Virtual memory access control
Page
Frame
Resident virtual pages
Page table
PTE
Page Frame Number (PFN)
Page Fault, Translation Not Valid (TNV)
Access Control Violation (ACV)
Process Page Table Base Register
Process Length Register
Translation Lookaside Buffer (TLB)
Content addressable memory (CAM)
Page Walk
X86 linear address
X86 page directory
X86 CR3
Intel variable page sizes
Cache Memory
Temporal & spatial locality
cache line (block)
Tag Store and Data Store
Tag Store Entry
Tag and index bits
Cache hit / miss
Direct mapped cache
Set-associative cache
Fully-associative cache
Cache set
Cache ways
Associative memory
Cache hit ratio
Virtually indexed, physically tagged cache
Cold start effect
Flushing the cache
Synonym problem
Write through cache
Write back cache
Allocate on write miss
Cache replacement policy
LRU replacement policy
Pseudo-LRU replacement policy
Separate instruction and data caches
Motorola 68020 - first cache
Page table
multiple levels of caches
Cache dirty bit
Prefetching
I/O parts: medium, device, controller
DMA
Polling vs interrupt driven I/O
Synchronous vs asynchronous bus
Handshaking
CSMA/CD
Bus master/slave
Multiplexed Address and Data Bus
Arbitration
Device controller
Central/distributed arbitration
Bus cycle
Request priority
Priority Arbitration Unit (PAU)
Bus request (BR)
Bus Grant (BG)
SACK
BBSY(Bus Busy)
MSYN (master sync)
SSYN (slave sync)
Daisy chain
RAID
Striping (in RAID)
RAID redundancy, performability
RAID Inexpensive/independent/interdependent
RAID coarse/fine
RAID parity
Mirroring