The University of Texas at Austin
Department of Electrical and Computer Engineering
EE 382N: Microarchitecture/Problem Sets/

Project Description

EE 382N – Spring 2022
Yale N. Patt, Instructor
Chester Cai, TAs

Fan out

When using the gates from the library, each gate is itself able to drive up to 4 other gates. If you need to drive more than 4 inputs buffering is required. We have provided several buffers in the library modules. Please adhere to the following rules while providing buffering:

  • The output is defined as the output of a gate OR the output of a behaviorally defined module in a lib file.
  • The input is defined as an input of a gate OR an input of a behaviorally defined module in a lib file.
  • No buffering is required if an output drives up to 4 inputs only. Buffering is required if an output drives more than 4 inputs.
  • You should buffer an output using bufferH16$ or bufferHInv16$ if the output drives upto 16 inputs only.
  • You should buffer an output using bufferH64$ or bufferHInv64$ if the output drives upto 64 inputs only.
  • You should buffer an output using bufferH256$ or bufferHInv256$ if the output drives upto 256 inputs only.
  • You should buffer an output using bufferH1024$ or bufferHInv1024$ if the output drives upto 1024 inputs only.
  • An output can drive ONLY ONE of the high-load buffer modules (i.e. bufferH16$, bufferHInv16$, bufferH64$, bufferHInv64$, bufferH245$, bufferHInv256$, bufferH1024$, bufferHInv1024$).
  • You should not be building your own buffer trees. If a need arises, please talk to us.

    • How to check for fan out

    While you could check for fan out by hand, we will be using synopsys design tools to do this.

    1. Log into the LRC server, run "module load synopsys/syn". This should load the synopsys design compiler
    2. Navigate to the directory containing the verilog files for your project
    3. Use the command "design_vision -no_gui" to open the dsign compiler
    4. To measure the fan out for a particular module, you need to add the verilog files for the module. Use the command "read_file -format verilog {verilog_files}" to the load the verilog files. Note you need to make sure that the top level module is the first file that you read in. You can also get around this by reading the file containing the top level module again.
    5. The above step may result in many warnings. This is the expected behavior. You should be fine as long as there are no errors. Do not load in the library files
    6. You can use the command "current_design" to make sure the top level module is the current design
    7. Finaly, use the command "all_high_fanout -nests -threshold 4". This will list all the wires with fanout greater than 4.

    Note from the TA

  • You may have heard that the fan out requirement is not really checked from previous semesters. However, we will be enforcing this requirement this semester.
  • Just like functional testing, you should check the fan out of your components as you finish them. You should not test fan out only at the end
  • You do not need to worry about the fanout for clock
  • The point of this exercise is to help you understand real design challenges. While this might feel like busy work, our hope is that you will develop the instinct to check for fan out whenever you add a wire/component to your design.