Fri, 24 Mar, 2023

    
        My students,

        As promised, I am attaching the figure I talked about in class yesterday
        dealing with virtual to physical address translation.  I am including the
        verbiage below to walk you through the figure:

        Assume I want to load the contents of X into R1.  As you know, addresses in
        your program are virtual addresses.  A virtual address consists of three parts:
        the region of virtual memory (in this case process space 00), the page number
        within virtual process space (assume in this case page A), and the page offset
        (in this case "y").  I can not read virtual memory so I need to know what
        frame (PFN) of physical memory contains page A.  (By the way, PFN stands for
        Page Frame Number.)  To do that I need the PTE of page A which contains the
        PFN.  We will assume we are unlucky and there is no entry in the TLB for page A.

        We know that all the PTEs comprise the Page Table, and are stored in virtual
        memory sequentially (PTE of page 0, PTE of page 1, etc.), starting with the
        PTE of page 0 at the location contained in the Process Base Register (PBR).
        That means the PTE of page A is stored at virtual address PBR + (4 times page
        number A).  (We multiply the page number by 4 since every PTE takes four bytes
        of memory.)  Since we know PBR and A, we can compute the address of the PTE of
        page A.  Let's say the PTE of page A is on page B of System Virtual Space. 
        Thus the virtual address of the PTE of page A is 10 (indicating system space),
        B (the system space page number), and z (the offset on page B).

        We can not read virtual memory so we need to find the physical frame that
        contains page B of System Space in order to read the PTA of Page A.  To get
        that frame, we need the PTE of page B, which is in the system page table. 
        Fortunately, the system page table is in physical memory.  The system page
        table is organized the same way as the process page table.  Therefore we can
        compute the address of the PTE of page B: SBR + (4 times page number B). 
        Since the system page table is in physical memory, the address of the PTE of
        page B is a physical address, so we can read the PTE.  The frame number in
        the PTE is the frame containing page B.  As shown in the figure, the frame
        number is M.  Knowing the frame number (M) and the offset on page B (z) we
        can construct the physical address of the PTE of page A.

        Now we can read the PTE of page A, and we see that page A is in Frame N.  Thus
        the address of X is byte y of frame N, which we can now read.  It contains the
        value 5, which we load into R1.

        One more thing.  You note that the PTEs of both pages A and B have their valid
        bits equal 1, indicating that pages A (in frame N) and B (in frame M) are both
        resident in physical memory.  If the valid bit of the PTE of page B were 0,
        Page B would not be resident so the microarchitecture would indicate a page
        fault.  The operating system would then bring page B into physical memory,
        which is necessary since page B contains the PTE of page A, which has the
        frame number of the frame containing page A.  If the valid bit of the PTE
        of Page A is 0, Page A is not resident in memory, so the value stored in X
        can not be read.  In this case also, the microarchitecture would signal a
        page fault, the operating system would then bring page A into physical memory,
        so X can be accessed.  Finally, X is read and its contents loaded into R1.

        Any questions, please let Kayvan, Michael, or me know.

        Enjoy the rest of the week.

        YNP            
    
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