Are we required to use ram cells for the tag store including valid, LRU, and dirty bits?
Yes, you have to use ram cells for both data and tag store. However, the valid, LRU, and dirty bits etc. can be implemented however you want.
How should the TLB be implemented?
The TLB structure can be implemented and initialized behaviorally using "regs" in your top module (1 reg per TLB entry for example). That way, it will be easy to change the TLB values if we wanted to. However, you must use structural verilog to implement the TLB lookup (i.e., the translation).
How many bytes do we push on the stack for the push imm8 instruction? Do we have to sign extend or zero extend?
If no operand size overide prefix is present, sign extend the 8-bit immediate to 32-bits and push the 32-bit value on the stack (ESP will be decremented by 4). If an operand size overide prefix is present, sign extend the 8-bit immediate to 16 bits, and push the 16-bit value on the stack (ESP will be decremented by 2).
Are tag and status bits included in the 1KB of total data storage for I-cache and D-cache?
No, the limitation is only for data (i.e., the data store). Other bits (e.g., tag, lru, dirty bit, or any extra buffer) do not count towards the 1K limit.
Are we allowed to add buffers to cache controller and memory side controller?
Yes. You are allowed 128 bytes of buffers on the cache side, and another 128 bytes of buffers on the memory side. A buffer is a structure that would improve the performance when there is a hit. This includes, but is not limited to victim cache, row buffers, store queue with forwarding.
What are the limitations of the bus?
The bus width is limited to 32 bits for data. In addition, you can have as many signals as you wish (for control, address, etc.) but they can not be used for data exchange.
Are there any requirements for the bus interface, can we implement a different bus for I/O ?
You are required to implement a single bus which connects the processor to memory and also to the I/O devices. The I/O devices must be memory mapped, so communication with I/O devices must be done through memory instructions. Remember to set the TLB bit to prevent the I/O pages from being cached.
The $readmemh function does not load my RAM! What do I do?
This seems to be a bug in VCS. The known workaround is to remove the top instance from the hierarchical path to the mem array to be loaded. For example, instead of TOP.dcache.data_store.ramcell[0].mem, try using dcache.data_store.ramcell[0].mem. Note that you should not load the RAMs in your final design, but you might want to do so during testing or debugging.
How does the CMPXCHG instruction affect condition codes?
The effect on ZF is described in the manual. The CF, PF, AF, SF, and OF condition codes are set based on the subtraction EAX − r/m32.
Should I use the SRAM module for the cache or can I use the RAM module?
Please use SRAM parts for main memory and RAM parts for the cache.
Can TLB values be changed during simulations?
No. TLB is only initialized at the beginning. Please expose the TLB values in the top module so that you can set them up easily.
Can PUSH or POP generate an exception?
These stack instructions consist of a stack access and, optionally, a POP
destination access or a PUSH source access. We assume that all stack space is in physical memory.
Thus the stack access cannot generate an exception. However, the POP
destination access or the PUSH source access can generate an exception.
Note that the segment override prefix applies
to the POP destination or the PUSH
source. The stack access always uses the SS segment.
Does REP CMPS allow interrupts or exceptions during execution?
Yes. A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the register is preserved to allow the string operation to be resumed upon a return from the exception or interrupt handler (see the manual for details)
Is it possible for the program stream to contain branch hints (2E, 3E) which would otherwise be recognized as CS, DS segment override prefixes?
For the project, you can assume that there are no branch hint prefixes.
How is the interrupt going to be generated for the testing of our designs?
The interrupt is generated by one of the I/O devices. To service this interrupt, your machine should do a context switch and execute the interrupt service routine (which can read from or write to the I/O device). Upon completion of the service routine, execution should be redirected to the original program.
Then how can the interrupt be tested since you don't know our I/O devices?
We do not provide the program for testing the interrupt. It is your job to write a test case that demonstrates that your machine can handle interrupts.
What is the size of each entry in IDT?
Each IDT entry has 64 bits. Thus, the starting address of the general protection exception handler will be stored in MEM[IDTR + 13 * 8] and the starting address of the page fault handler will be stored in MEM[IDTR + 14 * 8].
What is the maximum size of the segment?
Segment limit is 20 bits, which means a segment can be up to 1MB.
Can memory data accesses cross page boundaries?
Yes. You should support a memory access across the page boundaries. This means that if the data you are accessing is in two different pages and the pages are all in the TLB, the processor should get the data correctly by accessing both pages without generating a page fault.
How can we load initial data into the SRAM or ROM modules?
Please use $readmemb and $readmemh for initializing the memory modules.
$readmemb reads binary numbers from a text file and $readmemh reads
hexadecimal numbers.
The syntax is:
$readmemb("data_filename", memory_module_name.mem);
$readmemh("data_filename", memory_module_name.mem);