In this problem you will create two tools to speed up the process of creating your final project: a combinational logic generator, and a state machine generator.
The combinational logic generator will be a program (i.e., a script) that will turn a truth table into a structural verilog module using the standard cells we provide for your use (link to STDcell lib). We recommend you write the program in Python, but you can use any language you prefer.
Your tool is to accept a truth table (in whatever format you wish) as input, and produce as output a structural verilog module that implements the truth table, similar to what you did for problem 1b.
An example is provided (This is a 2-4 decoder).
What to turn in:
NOTE: We are looking for correctness, BUT its in your interest to go back and optimize your solution when you use this tool on the project. HINT: The espresso tool is capable of parsing a truth table and returning an optimized boolean expression.
The Moore model State Machine generator will be a program that takes as input a truth table representing a state machine, and produces as output a structural verilog module that implements the state machine using the standard cells we provide.
As in Part A, you are free to specify the format of the input as you wish and to program in any language you wish.
What to turn in: