Abstraction
Problem
Algorithm
Definiteness
Effective Computability
Language
Instruction Set Architecture (ISA)
Assembly Language
Microarchitecture/Implementation
Circuits
Electrons
Binary Digit (Bit)
ASCII (Codes)
Data Type
Data Types
2's complement
Sign Extension
ASCII
overflow
conversion
bit vector
NOT, AND, OR, XOR, etc.
floating point
Hexadecimal (Hex)
signed/unsigned integers
Bit Vector
Truth Table
NOT, AND, OR, XOR functions
Logically complete
Floating Point
Opcode
DeMorgan's Law
Hexadecimal (Hex)
Signed magnitude
Switch-level behavior
Gate, source, drain
N-type transistor
P-type transistor
MOSFET
CMOS
Logic gate
NAND, NOR, XOR gate
Equivalence Gate
Decoder
Multiplexer (Mux)
4-to-1 Mux
Select line
Full adder (or 1-bit adder)
AND-array
OR-array
Programmable logic array (PLA)
Combinational logic
Sequential logic
Latch
Gated latch
Write enable
Clock
Quiescent state
Address
Memory Address Register (MAR)
Memory Data Register (MDR)
Word Line
Addressability
Bit Line
State
Finite State Machine (FSM)
Asynchronous
Synchronous
Clock Cycle
Clock 
Transitions
Flip Flop
Master/Slave
Von Neumann
Memory
Address Space
Addressability
Byte
Word
Assembler
Compiler
Register
ALU
Input Device 
Control Unit
Instruction Cycle
Program Counter
Fetch
Decode
Execute
Write
Datapath
Timing diagram
ISA
Bus
PC, MAR, MDR, IR
Gate (bus)
Operate instruction
Data movement instruction
Control instruction
Immediate/literal
Addressing modes
Op-code
Trap Vector
State machine
BEN
NZP vs nzp
Condition codes
Structured programming
Systematic decomposition
Sequential
Iteration
Conditional
ASCII Code
HALT
Unconditional branch
Initialization
Predicate/Condition
Constants
OS Interface
LDR
Datapath
Base register