This is the last assignment that you will work on by yourself. Starting with problem set 5, you will be part of a group, and we will expect to see a single solution from the entire group.
In this problem set, you will create a simple processor that can execute four instructions in total. It is highly recommended to implement a pipelined processor. The instructions are shown below:
Design and draw out the datapath for a processor to handle these four instructions after decode. That is, the inputs to this design will be already decoded control signals. You should submit all the designs as well as a separate document explaining what each of your control signals do.
Please use structural Verilog to implement logic structures for the two test cases below based on your Part 1. Everything from register reading to writeback must be structural Verilog. Anything in fetch and decode can be implemented with behavioral Verilog and made as simple as possible.
Both of these programs are expected to finish successfully. Simulate your design and verify that it works for the sets and use DVE to monitor important data and control signals in the processor. Submit both your Verilog (including test benches) as well as a document containing screenshots that verify functionality of your design.
MOV EAX,0x12340000 // B8 00 00 34 12
MOV ECX,0x00001234 // B9 34 12 00 00
ADD EAX,ECX // 01 C8
ADD EAX,#-1 // 83 C0 FF
HLT // F4 MOV EAX, 0x12341234 // B8 34 12 34 12
JMP Down // E9 05 00 00 00
MOV EAX, 0xFADEDACE // B8 CE DA DE FA
Down ADD EAX, #1 // 05 01 00 00 00
HLT // F4