This assignment is to prepare your group for the initial design review of your course project. From now on, you will work as a group on the project through the end of the term. You can find the project page with full details here.
Take a first cut at the design of your CPU core that implements all the necessary instructions specified by the project description. This includes your pipeline stages, caches, TLBs, register files, control signals, and any other microarchitectural features in the pipeline.
Hand in the schematics created.
Take a first cut at the design of your off-core and memory system. Include all major functional blocks (e.g., main memory, exceptions, interrupts). Include necessary drawings and state machines for each part.
Hand in any diagrams and state machines.
Take a first cut at the design of an external bus interface. (You will need this to handle external interrupts, memory accesses, and I/O.) This should include a description of bus signals and bus protocols.
Hand in a description of the bus interface.
Construct a Gantt chart for the design of your machine. Each row of the Gantt chart should represent a task in your design process. The columns should represent time. Each task has a start time and a duration that you estimate as reasonable for the task. Each task should also identify the group member(s) responsible for the task. The design, test, and debug of each module of your machine is a separate task. The integration of smaller units into a larger unit is also a task. Make sure each module is working correctly in isolation before you connect it to other parts of the machine. Once you know that two modules work correctly in isolation, you can connect them together and test/debug the two modules together (i.e., test/debug the interface between the two modules, and how they work together). That combining operation is also a task. In your Gantt chart, pay special attention to the dependencies this creates between tasks. For example, you cannot test/debug a larger module that includes two sub-modules until you are sure that the sub-modules work correctly in isolation. Testing and debugging are extremely important. Be sure to allocate enough time in the task for testing and debugging the larger module.
You should not wait until the end of the semester to test/debug your machine. Allow yourself as much debugging time as possible. Note that testing and debugging a module is generally much more time-consuming than designing the module in the first place. It is important that you leave time at the end for final integration testing and debugging. You should also leave some time at the end for critical path analysis and redesign.
Here is a figure of what a Gantt chart looks like:
taskA | xxxxxxxx
taskB | xxxxxxxxx
taskC | xxxxxxxxx
... |
---------------------------------
| time ->
In your schedule, tasks A, B, and C should be reasonably detailed descriptions of what you will need to do to complete each task.
Your first Gantt chart will be due at the first design review. Every week you will be required to update your Gantt chart and hand it in along with the Gantt chart of all preceding weeks. If a component takes more time to design/test/debug than you estimated, all components that depend on that component need to be rescheduled accordingly. Conversely, if a component takes less time than you estimated, you can reallocate time to other components that can now start earlier.
Your group should sign up for an initial design review. This will take place on February 26th or February 27th in one of the conference rooms of the EER. We have allocated one hour for each design review. A sign-up sheet is posted on Professor Patt's office door (EER 5.802). All members of your group must attend the first design review. If no time slot is good for all the members of your group, please email Orhan and we will make other arrangements to accommodate your schedules.
Please bring one paper copy of all documents to the design review.