cpu_cycles: process
   variable reg_mem, hw_interrupt, BR: Boolean;
   variable sign_ext: std_logic_vector(4 downto 0);

begin
reg_mem:= (mode = imm) or (mode = dir) or (mode = ext) or (mode = ix) or 
         (mode = ix1) or (mode = ix2);
hw_interrupt := (I = '0') and (IRQ = '1' or SCint = '1');

wait until rising_edge(CLK);
if (rst_b = '0') then ST <= reset; fill_memory(mem);
else 
case ST is
when reset => SP <= "111111";
	if (rst_b = '1') then ST <= cycle8; end if;
when fetch => 
  if reg_mem then ALU_OP(Md, A, X, N, Z, C); end if;	
		-- complete previous operation
  if hw_interrupt then ST <= push1;
      else  Opcode <= mem(CONV_INTEGER(PC)); PC <= PC+1;  -- fetch opcode
      ST <= addr1; end if;

when addr1 =>
   case mode is
      when inha => ALU1(A, N, Z, C);  ST <= fetch;	-- do operation on A
      when inhx => ALU1(X, N, Z, C);   ST <= fetch;	-- do operation on X
      when imm => Md <= mem(CONV_INTEGER(PC));	-- get immediate data
         PC <= PC+1; ST <= fetch;
      when inh1 =>  
         if OP = SWI then ST <= push1;
           elsif OP = RTS then ST<= pop2; SP <= SP+1;
           elsif OP = RTI then ST <= pop5; SP <= SP+1;
         end if;
      when inh2 =>
         case OP is
            when TAX =>  X <= A;
            when CLC =>  C <= '0';
            when SEC => C <= '1';
            when CLI =>  I <= '0';
            when SEI => I <= '1';
            when RSP => SP <= "111111";
            when TXA => A <= X;
            when others => 
		assert(false) report "illegal instruction, mode = inh2";
         end case;
         ST <= fetch;
      when dir =>
          if OP = JMP then PC <= zero&mem(CONV_INTEGER(PC)); ST <= fetch;
          else MAR <= zero&mem(CONV_INTEGER(PC)); PC <=PC+1;	
						-- get direct address
          		if (OP=JSR) then  ST <= push1; else ST <= data; end if;
          end if;
			...   (remainder of process omitted - see Appendix D)