library ieee;
use ieee.std_logic_1164.all;

entity m68hc05 is
port(clk, rst_b, irq, RxD : in std_logic;
		PortA, PortB : inout std_logic_vector(7 downto 0);
		TxD : out std_logic);
end m68hc05;

architecture M6805_64 of m68hc05 is
component cpu6805
port(clk, rst_b, IRQ, SCint: in std_logic;
	dbus : inout std_logic_vector(7 downto 0);
	abus : out std_logic_vector(12 downto 0);
	wr: out std_logic);
end component;

component ram32X8_io
port (addr_bus: in std_logic_vector(4 downto 0);
			data_bus: inout std_logic_vector(7 downto 0);
			cs, cpu_wr: in  std_logic);
end component;

component PORT_A
port(clk, rst_b, Port_Sel, ADDR0, R_W : in std_logic;
		DBUS : inout std_logic_vector(7 downto 0);
		PinA : inout std_logic_vector(7 downto 0));
end component;

component UART
port(SCI_sel, R_W, clk, rst_b, RxD : in std_logic;
	ADDR2: in std_logic_vector(1 downto 0);
	DBUS : inout std_logic_vector(7 downto 0);
	SCI_IRQ, TxD : out std_logic);
end component ;

signal SCint, wr, cs1, cs2, we: std_logic;
signal SelLowRam, SelHiRAM, SelPA, SelPB, SelSC : std_logic;
signal addr_bus: std_logic_vector(12 downto 0) := (others => '0');
signal data_bus: std_logic_vector(7 downto 0) := (others => '0');

begin
CPU: cpu6805 port map (clk, rst_b, irq, SCint, data_bus, addr_bus, wr);
PA: PORT_A port map (clk, rst_b, SelPA, addr_bus(0), wr, data_bus, PortA);
PB: PORT_A port map (clk, rst_b, SelPB, addr_bus(0), wr, data_bus, PortB);
Uart1: UART port map (SelSC, wr, clk, rst_b, RxD, addr_bus(1 downto 0),
					 data_bus, SCint, TxD);
LowRAM: ram32X8_io port map (addr_bus(4 downto 0), data_bus, cs1, we);
HiRAM:  ram32X8_io port map (addr_bus(4 downto 0), data_bus, cs2, we);

-- memory interface
cs1 <= SelLowRam and not clk; 	-- select ram on 2nd half of clock cycle
cs2 <= SelHiRam and not clk; 
we <= wr and not clk;					-- write enable on 2nd half of clock cycle

-- address decoder
SelPA <= '1' when addr_bus(12 downto 1) = "000000000000" else '0';   	
SelPB <= '1' when addr_bus(12 downto 1) = "000000000001" else '0';
SelSC <= '1' when addr_bus(12 downto 2) = "00000000001"  else '0';	
SelLowRam <= '1' when addr_bus(12 downto 5) = "00000001" else '0';
--		32 <= addr <= 63
SelHiRam <= '1'  when addr_bus(12 downto 5) = "11111111" else '0';
--		addr >= 8160 (1FE0h)
end M6805_64;