entity SM1_2 is
	port (X, CLK: in bit;
		Z: out bit);
end SM1_2;

architecture Table of SM1_2 is
	type StateTable is array (integer range <>, bit range <>) of integer;
	type OutTable is array (integer range <>, bit range <>) of bit;
	signal State, NextState: integer := 0;
	constant ST: StateTable (0 to 6, '0' to '1') :=
		((1,2), (3,4), (4,4), (5,5), (5,6), (0,0), (0,0));
	constant OT: OutTable (0 to 6, '0' to '1') :=
		(('1','0'), ('1','0'), ('0','1'), ('0','1'), ('1','0'), ('0','1'), 
		('1','0'));
begin						-- concurrent statements
	NextState <= ST(State,X);		-- read next state from state table
	Z <= OT(State, X);			-- read output from output table
	process(CLK)
	begin
		if CLK = '1' then		-- rising edge of CLK
			State <= NextState;
		end if;
	end process;
end Table;