library BITLIB;
use BITLIB.bit_pack.all;

entity c74163test is
	port(ClrN,LdN,P,T1,Clk: in bit;
		Din1, Din2: in bit_vector(3 downto 0);
		Qout1, Qout2: inout bit_vector(3 downto 0);
		Carry2: out bit);
end c74163test;

architecture tester of c74163test is
	component c74163
	   port(LdN, ClrN, P, T, CK: in bit;  D: in bit_vector(3 downto 0);
	   Cout: out bit; Q: inout bit_vector(3 downto 0) );
	end component;
	signal Carry1: bit;
	signal Count: integer;
	signal temp: bit_vector(7 downto 0);
begin
	ct1: c74163 port map (LdN,ClrN,P,T1,Clk,Din1,Carry1,Qout1);
	ct2: c74163 port map (LdN,ClrN,P,Carry1,Clk,Din2,Carry2,Qout2);
	temp <= Qout2 & Qout1;
	Count <= vec2int(temp);
end tester;