library ieee;
use ieee.std_logic_1164.all;		-- IEEE standard logic package
library MVLLIB;				-- includes PLAmtrx type and 
use MVLLIB.mvl_pack.all;		--    PLAout function

entity PLA1_2 is
  port(X,CLK: in std_logic;
       Z: out std_logic);
end PLA1_2;

architecture PLA of PLA1_2 is
signal Q, Qplus: std_logic_vector(1 to 3) := "000";
constant FSM_PLA:  PLAmtrx(0 to 6, 7 downto 0) := 
                ("X0XX1000",
                 "1XXX0100",
                 "111X0010",
                 "1X000010",
                 "00X10010",
                 "XX000001",
                 "XX110001");
begin
  process(Q,X)
  variable PLAValue: std_logic_vector(3 downto 0);
  begin
    PLAValue := PLAout(FSM_PLA,Q & X);     -- read PLA output
    Qplus <= PLAValue(3 downto 1);
    Z <= PLAValue(0);
  end process;


  process(CLK)
  begin
    if CLK='1' then Q <= Qplus; end if;   -- update state register
  end process;
end PLA;