entity traffic_light is
	port (clk, Sa, Sb: in bit;
			Ra, Rb, Ga, Gb, Ya, Yb: inout bit);
end traffic_light;

architecture behave of traffic_light is
	signal state, nextstate: integer range 0 to 12;
	type light is (R, Y, G);
	signal lightA, lightB: light;  -- define signals for waveform output
begin
	process(state, Sa, Sb)
	begin
		Ra <= '0'; Rb <= '0'; Ga <= '0'; Gb <= '0'; Ya <= '0'; Yb <= '0';
		case state is
			when 0 to 4 => Ga <= '1'; Rb <= '1'; nextstate <= state+1;
			when 5 => Ga <= '1'; Rb <= '1'; 
						 if Sb = '1' then nextstate <= 6; end if;
			when 6 => Ya <= '1'; Rb <= '1'; nextstate <= 7;
			when 7 to 10 => Ra <= '1'; Gb <= '1'; nextstate <= state+1;
			when 11 => Ra <= '1'; Gb <= '1'; 
						  if (Sa='1' or Sb='0') then nextstate <= 12; end if;
			when 12 => Ra <= '1'; Yb <= '1'; nextstate <= 0;
		end case;
	end process;
	process(clk)
	begin 
		if clk = '1' then
			state <= nextstate;
		end if; 
	end process;
	lightA <= R when Ra='1' else Y when Ya='1' else G when Ga='1';
	lightB <= R when Rb='1' else Y when Yb='1' else G when Gb='1'; 
end behave;