library BITLIB;
use BITLIB.bit_pack.all;

entity testmult is
end testmult;

architecture test1 of testmult is
component mult2C
        port(CLK, St: in bit;
              Mplier,Mcand : in bit_vector(3 downto 0);
              Product: out bit_vector (6 downto 0);
              Done: out bit);
end component;

  constant N: integer := 11;
  type arr is array(1 to N) of bit_vector(3 downto 0);
  constant Mcandarr: arr := ("0111", "1101", "0101", "1101", "0111", "1000", 	"0111", "1000", "0000", "1111", "1011");
  constant Mplierarr: arr := ("0101", "0101", "1101", "1101", "0111", 	"0111", "1000", "1000", "1101", "1111", "0000");
  signal CLK, St, Done: bit;
  signal Mplier, Mcand: bit_vector(3 downto 0);
  signal Product: bit_vector(6 downto 0);
begin
  CLK <= not CLK after 10 ns;
  process
  begin
    for i in 1 to N loop
      Mcand <= Mcandarr(i);
      Mplier <= Mplierarr(i);
      St <= '1';
      wait until rising_edge(CLK);
      St <= '0';
      wait until falling_edge(Done);
    end loop;  
  end process;
  mult1: mult2c port map(Clk, St, Mplier, Mcand, Product, Done);
end test1;