entity Fig_4_6 is
	port (St, K, M, CLK : in bit;
			Ad, Sh, Load, Done : out bit);
end Fig_4_6;

architecture CLBs of Fig_4_6 is
	component XC4000CLB
		port(MEM_BITS : in bit_vector(0 to 51);
				G_IN, F_IN, C_IN : in bit_vector(4 downto 1);
				K : in bit;
				Y,X : out bit;
				Q : out bit_vector (1 downto 0));
	end component;

	constant MEM1 : bit_vector (0 to 51) :=
			"0000010001100110011000101110101000000000100100110000";
	constant MEM2 : bit_vector (0 to 51) :=
			"0001000100010001000000001000100000000000000000110000";
	constant MEM3 : bit_vector (0 to 51) :=
			"0000000001000100011001100010001000000000000000110000";

	signal Q : bit_vector (1 downto 0);
	signal G_IN1,G_IN2,G_IN3,F_IN1,F_IN2,F_IN3 : bit_vector (3 downto 0);

begin
	G_IN1<=K&M&Q; F_IN1<=St&M&Q;
	G_IN2<="00"&Q; F_IN2<=St&'0'&Q;
	G_IN3<=M&'0'&Q; F_IN3<=M&'0'&Q;

	CLB1: XC4000CLB port map (MEM1,G_IN1,F_IN1,"1000",CLK,open,open,Q);
	CLB2: XC4000CLB port map (MEM2,G_IN2,F_IN2,"1000",CLK,Done,Load,open);
	CLB3: XC4000CLB port map (MEM3,G_IN3,F_IN3,"1000",CLK,Ad,Sh,open);
end CLBs;