library ieee;
use ieee.std_logic_1164.all;
library mvllib;
use mvllib.mvl_pack.all;

entity Platest is 
port (ABC: in std_logic_vector(2 downto 0);
      F: out std_logic_vector(3 downto 0));
 end Platest;

architecture PLA1 of PLAtest is
constant PLA3_2: PLAmtrx (0 to 4, 6 downto 0) :=
	("00X1010", "1X01100", "X1X0101", "X100010", "1X10001");
begin 
F<= PLAout (PLA3_2, ABC);
end PLA1;