entity SM1_2 is
   port(X, CLK: in bit;
        Z: out bit);
end SM1_2;

architecture Table of SM1_2 is
   subtype s_type is integer range 0 to 7;
   signal State, Nextstate: s_type;
   constant S0: s_type := 0; -- state assignment
   constant S1: s_type := 4;
   constant S2: s_type := 5;
   constant S3: s_type := 7;
   constant S4: s_type := 6;
   constant S5: s_type := 3;
   constant s6: s_type := 2;
begin
   process(State,X)					--Combinational Network
   begin
     Z <= '0'; Nextstate <= S0;			-- added to avoid latch		
     case State is
      when S0 =>
         if X='0' then Z<='1'; Nextstate<=S1;
         else Z<='0'; Nextstate<=S2;  end if;
      when S1 =>
         if X='0' then Z<='1'; Nextstate<=S3;
         else Z<='0'; Nextstate<=S4; end if; 
      when S2 =>
         if X='0' then Z<='0'; Nextstate<=S4;
         else Z<='1'; Nextstate<=S4; end if; 
      when S3 =>
         if X='0' then Z<='0'; Nextstate<=S5;
         else Z<='1'; Nextstate<=S5;  end if;
      when S4 =>
         if X='0' then Z<='1'; Nextstate<=S5;
         else Z<='0'; Nextstate<=S6; end if;
      when S5 =>
         if X='0' then Z<='0'; Nextstate<=S0;
         else Z<='1'; Nextstate<=S0; end if; 
      when S6 =>
         if X='0' then Z<='1'; Nextstate<=S0; end if;
      when others => null;
     end case;
  end process;

  process(CLK)                          -- State Register
    begin
     if CLK='1' and CLK'event then      -- rising edge of clock
       State <= Nextstate;
     end if;
  end process;
end Table;