-- Simple memory model
library IEEE;
use IEEE.std_logic_1164.all;
library BITLIB;
use BITLIB.bit_pack.all;

entity RAM6116 is
	port(Cs_b, We_b: in bit;
		Address: in bit_vector(7 downto 0);
		IO: inout std_logic_vector(7 downto 0));
end RAM6116;

architecture simple_ram of RAM6116 is 
	type RAMtype is array(0 to 255) of std_logic_vector(7 downto 0);
	signal RAM1: RAMtype:=(others=>(others=>'0')); 
								-- Initialize all bits to '0'
begin
	process
	begin
		if Cs_b = '1' then IO <= "ZZZZZZZZ";	-- chip not selected
		else
			if We_b'event and We_b = '1' then 	-- rising-edge of We_b
				RAM1(vec2int(Address'delayed)) <= IO; 	-- write
				wait for 0 ns;				-- wait for RAM update
			end if;
			if We_b = '1' then 
				IO <= RAM1(vec2int(Address));  	--read
			else IO <= "ZZZZZZZZ";  			--drive high-Z
			end if;
		end if;
		wait on We_b, Cs_b, Address;
	end process;
end simple_ram;