library IEEE;
use IEEE.std_logic_1164.all;
library BITLIB;
use BITLIB.bit_pack.all;

entity RAM_timing_tester is
end RAM_timing_tester;

architecture test1 of RAM_timing_tester is

  component static_RAM is
	port (CS_b, WE_b, OE_b: in bit;
		Address: in bit_vector(7 downto 0);
		Data: inout std_logic_vector(7 downto 0));
  end component Static_RAM;

  signal Cs_b, We_b: bit := '1';		-- active low signals
  signal Data: std_logic_vector(7 downto 0) := "ZZZZZZZZ";
  signal Address: bit_vector(7 downto 0);

begin
	SRAM1: Static_RAM port map(Cs_b, We_b, '0', Address, Data);
	process
	begin
		wait for 100 ns;				

		Address <= "00001000"; 				-- WE-controlled write
		Cs_b <= '0'; 
		We_b <= transport '0' after 20 ns;
		Data <= transport "11100011" after 140 ns;
		Cs_b <= transport '1' after 200 ns;
		We_b <= transport '1' after 180 ns;
		Data <= transport "ZZZZZZZZ" after 220 ns;
		wait for 200 ns;				

		Address <= "00011000"; 				-- RAM deselected
		wait for 200 ns;

		Address <= "00001000";				-- Read cycles
		Cs_b <= '0';
		wait for 200 ns;
		Address <= "00010000";
		Cs_b <= '1' after 200 ns;
		wait for 200 ns;
		
		Address <= "00011000";				-- RAM deselected
		wait for 200 ns;
	end process;
end test1;