-- Tester for Bus model
library BITLIB;
use BITLIB.bit_pack.all;
use std.textio.all;

entity tester is
	port ( address, w_data: out bit_vector(31 downto 0);
		r_data: in bit_vector(31 downto 0);
		clk, wr, br: out bit;
		std, done: in bit := '0');
end tester;

architecture test1 of tester is
	constant half_period: time := 10 ns;		-- 20 ns clock period
	signal testclk: bit := '1';
begin
	testclk <= not testclk after half_period;
	clk <= testclk after 1 ns;				-- Delay bus clock
	read_test_file: process(testclk)
		file test_file: text open read_mode is "test2.dat";
		variable buff: line;
		variable dataint, addrint: integer;
		variable new_wr, new_br: bit;
	begin
	if testclk = '1' and done = '1' then
		if std = '1' then 
			assert dataint = vec2int(r_data)
				report "Read data doesn't match data file!"
				severity error;
		end if;	
		if not endfile(test_file) then
			readline(test_file, buff);
			read(buff, new_br);
			read(buff, new_wr);
			read(buff, addrint);
			read(buff, dataint);
			br <= new_br;
			wr <= new_wr;
			address <= int2vec(addrint,32);
			if new_wr = '1' and new_br = '1' then 
				w_data <= int2vec(dataint,32);
			else w_data <= (others => '0');
			end if;
		end if;
	end if;
	end process read_test_file;	
end test1;