library IEEE;
use IEEE.std_logic_1164.all;
entity i486_bus_sys is
end i486_bus_sys;

architecture bus_sys_bhv of i486_bus_sys is
--************************************************************
--                              COMPONENTS
--************************************************************
component i486_bus
	 port (		--external interface
		abus: out bit_vector(31 downto 0);
		dbus: inout std_logic_vector(31 downto 0);
		w_rb, ads_b: out bit;
		rdy_b, clk: in bit;
			--internal interface
		address, w_data: in bit_vector(31 downto 0);
		r_data: out bit_vector(31 downto 0);
		wr, br: in bit;
		std, done:out bit);
end component;
component static_RAM
	generic (constant tAA,tACS,tCLZ,tCHZ,tOH,tWC,tAW,tWP,tWHZ,tDW,tDH,tOW: 							  	time);  
	port (	CS_b, WE_b, OE_b: in bit;
		Address: in bit_vector(7 downto 0);
 		Data: inout std_logic_vector(7 downto 0));
end component;
component memory_control
	port(	clk, w_rb, ads_b, cs1: in bit;
		rdy_b, we_b, cs_b: out bit);
end component;
component tester
	port (	address, w_data: out bit_vector(31 downto 0);
		r_data: in bit_vector(31 downto 0);
		clk, wr, br: out bit;
		std, done: in bit);
end component;
--                          SIGNALS
--************************************************************
	constant decode_delay: time := 5 ns;
	constant addr_decode: bit_vector(31 downto 8) := (others => '0');
	signal cs1: bit;
	--signals between tester and bus interface unit
	signal address, w_data, r_data: bit_vector(31 downto 0);
	signal clk, wr, br, std, done: bit;
	--external 486 bus signals
	signal w_rb, ads_b, rdy_b: bit;
	signal abus: bit_vector(31 downto 0); 
	signal dbus: std_logic_vector(31 downto 0);
	--signals to RAM
	signal cs_b, we_b: bit;
--************************************************************
begin
	bus1: i486_bus port map (abus, dbus, w_rb, ads_b, rdy_b, clk, address, 								   w_data, r_data, wr, br, std, done);
	control1: memory_control port map (clk, w_rb, ads_b, cs1, rdy_b, we_b, 										 cs_b);
	RAM32: for i in 3 downto 0 generate
		ram: static_RAM 
			generic map(25 ns,25 ns,3 ns,3 ns,3 ns,25 ns,15 ns,15 ns,10 ns,12 ns,
							 0 ns,0 ns)
			port map(cs_b, we_b, '0', abus(7 downto 0), dbus(8*i+7 downto 8*i));
	end generate RAM32;
	test: tester port map(address, w_data, r_data, clk, wr, br, std, done);
--********************************************************************
	-- Address decoder signal sent to memory controller
	cs1 <= '1' after decode_delay when (abus(31 downto 8) = addr_decode)
		else '0' after decode_delay;
--********************************************************************
end bus_sys_bhv;