Assembly Reference

Jonathan Valvano and Ramesh Yerraballi

Our purpose in writing this book is not to provide a complete description of the ARM® CortexÔ M or any TM4C microcontroller. Rather the book is a learning tool for first year college students majoring in engineering and science. As such, this appendix is not a complete list of all Thumb instructions. It gives details on the subset of instructions introduced in this book. Depending on exactly how you count, the Cortex M processor has over 150 instructions. However, we think this subset of 30 instructions will be sufficient to perform the homework and labs associated with the book. On the other hand, these three are complete reference manuals for the Cortex-M processor. They are available as pdf files linked below.

Quick Reference Assembly Guide (ARM)
Cortex-M3/M4F Instruction Set (Texas Instruments)
The ARM Cortex-M Technical Reference Manual (ARM)

Memory access instructions
   LDR Rd, [Rn] ; load 32-bit number at [Rn] to Rd
   LDRH Rd, [Rn] ; load unsigned 16-bit at [Rn] to Rd
   LDRSH Rd, [Rn] ; load signed 16-bit at [Rn] to Rd
   LDRB Rd, [Rn] ; load unsigned 8-bit at [Rn] to Rd
   LDRSB Rd, [Rn] ; load signed 8-bit at [Rn] to Rd
   STR Rt, [Rn] ; store 32-bit Rt to [Rn]
   STRH Rt, [Rn] ; store least sig. 16-bit Rt to [Rn]
   STRB Rt, [Rn] ; store least sig. 8-bit Rt to [Rn]
   PUSH {Rt} ; push 32-bit Rt onto stack
   POP {Rd} ; pop 32-bit number from stack into Rd
   ADR Rd, label ; set Rd equal to the address at label
   MOV Rd, #im16 ; set Rd equal to im16, im16 is 0 to 65535
   MVN Rd, op2 ; set Rd equal to -op2
Branch instructions
   B label ; branch to label Always
   BEQ label ; branch if Z == 1 Equal
   BNE label ; branch if Z == 0 Not equal
   BCS label ; branch if C == 1 Higher or same, unsigned ≥
   BHS label ; branch if C == 1 Higher or same, unsigned ≥
   BCC label ; branch if C == 0 Lower, unsigned <
   BLO label ; branch if C == 0 Lower, unsigned <
   BMI label ; branch if N == 1 Negative
   BPL label ; branch if N == 0 Positive or zero
   BVS label ; branch if V == 1 Overflow
   BVC label ; branch if V == 0 No overflow
   BHI label ; branch if C==1 and Z==0 Higher, unsigned >
   BLS label ; branch if C==0 or Z==1 Lower or same, unsigned ≤
   BGE label ; branch if N == V Greater than or equal, signed ≥
   BLT label ; branch if N != V Less than, signed <
   BGT label ; branch if Z==0 and N==V Greater than, signed >
   BLE label ; branch if Z==1 or N!=V Less than or equal, signed ≤
   BX Rm ; branch indirect to location specified by Rm
   BL label ; branch to subroutine at label, return address in LR
   BLX Rm ; branch to subroutine indirect specified by Rm
Interrupt instructions
   CPSIE I ; enable interrupts (I=0)
   CPSID I ; disable interrupts (I=1)
Logical instructions
   AND Rd, Rn, op2 ; Rd=Rn&op2 (op2 is 32 bits)
   ORR Rd, Rn, op2 ; Rd=Rn|op2 (op2 is 32 bits)
   EOR Rd, Rn, op2 ; Rd=Rn^op2 (op2 is 32 bits)
   BIC Rd, Rn, op2 ; Rd=Rn&(~op2) (op2 is 32 bits)
   ORN Rd, Rn, op2 ; Rd=Rn|(~op2) (op2 is 32 bits)
   LSR Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned)
   ASR Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed)
   LSL Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned)
Arithmetic instructions
   ADD Rd, Rn, op2 ; Rd = Rn + op2
   SUB Rd, Rn, op2 ; Rd = Rn - op2
   RSB Rd, Rn, op2 ; Rd = op2 - Rn
   CMP Rn, op2 ; Rn – op2 sets the NZVC bits
   CMN Rn, op2 ; Rn - (-op2) sets the NZVC bits
   MUL Rd, Rn, Rm ; Rd = Rn * Rm signed or unsigned
   MLA Rd, Rn, Rm, Ra ; Rd = Ra + Rn*Rm signed or unsigned
   MLS Rd, Rn, Rm, Ra ; Rd = Ra - Rn*Rm signed or unsigned
   UDIV Rd, Rn, Rm ; Rd = Rn/Rm unsigned
   SDIV Rd, Rn, Rm ; Rd = Rn/Rm signed

ADR

Load PC-relative address

Syntax

ADR{cond} Rd, label

where {cond} is an optional condition code. Rd Is the destination register. label is a PC-relative expression.

Operation

ADR determines the address by adding an immediate value to the PC, and writes the address of the label to the destination register. ADR produces position-independent code, because the address is PC-relative. If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to 1 for correct execution. Values of label must be within the range of -4095 to +4095 from the address in the PC. You might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-aligned. See the instruction manual for more information about .W width selection.

Restrictions

Rd must not be SP and must not be PC.

Condition Flags

This instruction does not change the flags.

Examples

Hello PUSH {R4,LR}

ADR R0, Name ;R0 is the address of the string at Name

BL OutString ;Print welcome

POP {R4,PC}

Name DCB "Hello world",0

AREA DATA

FuncPt SPACE 4

AREA CODE,READONLY,ALIGN=2

Set ADR R0, Hello ;R0 points to function Hello

ORR R0,R0,#1 ;set Thumb bit (this step IS necessary)

LDR R1,=FuncPt

STR R0,[R1] ;FuncPt points to Hello

BX LR

ADD

32-bit Addition

Syntax

ADD{S}{cond} {Rd,} Rn, Op2

ADD{cond} {Rd,} Rn, #imm12

where {S} is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation. {cond} is an optional condition code. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the first operand. Op2 is a flexible second operand. imm12 is any value in the range 0–4095. The syntax of Op2 is

ADD Rd, Rn, Rm ; op2 = Rm

ADD Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

ADD Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

ADD Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

ADD Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The ADD instruction adds the value of Op2 or imm12 to the value in Rn and stores the sum in Rd.

Rd = Rn + Op2

Rd = Rn + imm12

Restrictions (for additional restrictions about PC see data sheet)

Op2 must not be SP and must not be PC.
Rd can be SP only with the additional restrictions:

Rn must also be SP.
any shift in Op2 must be limited to a maximum of 3 bits using LSL.

Condition Flags

If S is specified, these instructions update the N, Z, C and V flags according to the result. R=X+M, where X is initial register value, M is the flexible second operand or the #imm12 constant, and R is the final register value.

N: result is negative N = R₃₁

Z: result is zero

V: signed overflow

C: unsigned overflow

Examples

ADD R2, R1, R3 ;R2=R1+R3

ADDS R4, R4, #100 ;R4=R4+100, set flags

ADDHI R11, R0, R3 ;R11=R0+R3, part of IT, execute if C=0 and Z=0

AND

32-bit Logical AND

Syntax

AND{S}{cond} {Rd,} Rn, Op2

AND Rd, Rn, Rm ; op2 = Rm

AND Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

AND Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

AND Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

AND Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The AND instruction performs a 32-bit bitwise AND operation on the values in Rn and Op2 and places the results into Rd. The AND instruction is useful for selecting bits. You specify which bits to select in the Op2.

Rd = Rn & Op2

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Examples

AND R9, R2, #0xFF00 ;R9=R2&0x0000FF00

AND R0, R0, R5 ;R0=R0&R5

AND R0, R0, R5, LSR #3 ;R0=R0&(R5<<3)

ANDS R9, R8, #1 ;R9=R8&0x00000001, sets flags

ANDHS R11, R0, R3 ;R11=R0&R3, part of IT, execute if C=0

ASR

32-bit Arithmetic Shift Right

Syntax

ASR{S}{cond} Rd, Rm, Rs

ASR{S}{cond} Rd, Rm, #n

where {S} is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation. {cond} is an optional condition code. Rd is the destination register. Rd cannot be omitted. Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte of Rs is used and can be in the range 0 to 255. n is the shift length (1 to 32).

Operation

ASR moves the bits in the register Rm to the right by the number of places specified by constant n or register Rs. Values are signed integers, so the sign bit in bit 31 is preserved. The result is written to Rd, and the value in register Rm remains unchanged.

Rd = Rm >> Rs (signed)

Rd = Rm >> n (signed)

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, these instructions update the N and Z flags according to the result in Rd. The C flag is updated to the last bit shifted out, except when the shift length is 0.

N: result is negative N = R₃₁

Z: result is zero

Examples

ASR R7, R8, #9 ;R7 = R8>>9, signed, (similar to R7 = R8/512)

ASR R0, R1, R2 ;R0 = R1>>R2, signed (similar to R0 = R1/2^R2)

ASRS R1, R2, #3 ;R1 = R2>>3, signed, with flag update

ASREQ R4, R5, #6 ;part of IT, if Z=1 then R4=R5>>6, signed

Branch instructions

Syntax

B label ; branch to label Always

BEQ label ; branch if Z == 1 Equal

BNE label ; branch if Z == 0 Not equal

BCS label ; branch if C == 1 Higher or same, unsigned ≥

BHS label ; branch if C == 1 Higher or same, unsigned ≥

BCC label ; branch if C == 0 Lower, unsigned <

BLO label ; branch if C == 0 Lower, unsigned <

BMI label ; branch if N == 1 Negative

BPL label ; branch if N == 0 Positive or zero

BVS label ; branch if V == 1 Overflow

BVC label ; branch if V == 0 No overflow

BHI label ; branch if C==1 and Z==0 Higher, unsigned >

BLS label ; branch if C==0 or Z==1 Lower or same, unsigned ≤

BGE label ; branch if N == V Greater than or equal, signed ≥

BLT label ; branch if N != V Less than, signed <

BGT label ; branch if Z==0 and N==V Greater than, signed >

BLE label ; branch if Z==1 or N!=V Less than or equal, signed ≤

where {cond} is an optional condition code.

Operation

These instructions cause a branch to label. These are the only conditional instructions that can be either inside or outside an IT block. All other conditional instructions must be inside an IT block.

B label -16 MB to +16 MB

Bcond label -1 MB to +1 MB (outside IT block)

Bcond label -16 MB to +16 MB (inside IT block)

You might have to use the .W suffix to get the maximum branch range. See the instruction manual for more information about .W width selection.

Restrictions

When inside an IT block, it must be the last instruction of the IT block.

Condition Flags

These instructions do not change the flags.

Examples

B loopA ;Branch to loopA

BLE ng ;Conditionally branch to label ng

B.W target ;Branch to target within 16MB range

BEQ target ;Conditionally branch to target

BEQ.W target ;Conditionally branch to target within 1MB

BIC

32-bit Logical Bit Clear

Syntax

BIC{S}{cond} {Rd,} Rn, Op2

BIC Rd, Rn, Rm ; op2 = Rm

BIC Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

BIC Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

BIC Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

BIC Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The BIC instruction performs a 32-bit bitwise AND operation on the bits in Rn with the complements of the corresponding bits from Op2 and places the results into Rd. This instruction is useful for clearing bits. You specify which bits to clear in the Op2.

Rd = Rn & ~Op2

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Examples

BIC R9, R2, #0xFF00 ;R9 = R2&0xFFFF00FF, clear bits 15-8

BICS R0, R0, #2 ;R0 = R0&0xFFFFFFFD, clear bit1, set flags

BIC R1, R2, R3, LSL #2 ;R1 = R2&(~(R3<<2))

BICEQ R2, R0, R5 ;R2 = R0&(~R5), part of IT execute if Z=1

Branch link (call subroutine)

Syntax

BL{cond} label ; branch to subroutine at label

where {cond} is an optional condition code. label is a PC-relative expression.

Operation

BL is the call to subroutine instruction. The address of the subroutine is specified by the label. The BL instruction also saves the return address (the address of the next instruction) in the Link Register (LR), Register R14. The range of the BL instruction is -16 MB to +16 MB from the current instruction. You might have to use the .W suffix to get the maximum branch range. See the instruction manual for more information about .W width selection.

Restrictions

Conditional execution can only occur inside an IT block.
When inside an IT block, it must be the last instruction of the IT block.

Condition Flags

This instruction does not change the flags.

Examples

BL Func ;Call to Func, return address in LR

MOV R0,#1234

MOV R1,#100

BL.W Divide ;Call to Divide, return address in LR (-16 to +16MB)

;example subroutine

Func PUSH {R4-R8,LR} ;save registers

;body of subroutine

POP {R4-R8,PC} ;restore registers and return

; find the unsigned quotient and remainder

; Inputs: dividend in R0

; divisor in R1

; Outputs: quotient in R2

; remainder in R3

;dividend = divisor*quotient + remainder

Divide

UDIV R2,R0,R1 ;R2=R0/R1, R2 is quotient

MUL R3,R2,R1 ;R3=(R0/R1)*R1

SUB R3,R0,R3 ;R3=R0%R1, R3 is remainder of R0/R1

BX LR ;return

BLX

Branch link indirect (call subroutine)

Syntax

BLX{cond} Rm ; branch to subroutine indirect specified by Rm

where {cond} is an optional condition code. Rm is a register that indicates the address to which to branch. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0.

Operation

BLX is an indirect call to subroutine instruction. The address of the subroutine is specified by the register Rm. The BLX instruction also saves the return address (the address of the next instruction) in the Link Register (LR), register R14.

Restrictions

Conditional execution can only occur inside an IT block.
It must be unconditional outside the IT block.
Do not use PC in the BLX instruction.
Bit[0] of Rm must be 1, the target address is created by changing bit[0] to 0.
When inside an IT block, it must be the last instruction of the IT block.

Condition Flags

This instruction does not change the flags.

Examples

FList DCD Fun0,Fun1,Fun2,Fun3 ;pointers to four functions

;Assume R2 contains a value from 0 to 3

LDR R1,=FList ;R1 points to list of functions

LDR R0,[R1,R2,LSL #2] ;R0 points to subroutine to execute

ORR R0,R0,#1 ;set thumb bit (this step may not be necessary)

BLX R0 ;call subroutine, return address in LR

;end of example

Fun0 ;body of function 0

BX LR

Fun1 ;body of function 1

BX LR

Fun2 ;body of function 2

BX LR

Fun3 ;body of function 3

BX LR

Branch indirect

Syntax

BX{cond} Rm ; branch indirect to location specified by Rm

where {cond} is an optional condition code. Rm is a register that indicates the address to which to branch.

Operation

This is a branch indirect instruction, with the branch address indicated in Rm. This instruction causes a UsageFault exception if bit[0] of Rm is 0. BX LR is often used as a return from subroutine.

Restrictions

Conditional execution can only occur inside an IT block.
It must be unconditional outside the IT block.
Bit[0] of Rm must be 1, the target address is created by changing bit[0] to 0.
When inside an IT block, it must be the last instruction of the IT block.

Condition Flags

This instruction does not change the flags.

Examples

; Inputs: dividend in R0

; divisor in R1

; Outputs: quotient in R2

; remainder in R3

;dividend = divisor*quotient + remainder

Divide

UDIV R2,R0,R1 ;R2=R0/R1, R2 is quotient

MUL R3,R2,R1 ;R3=(R0/R1)*R1

SUB R3,R0,R3 ;R3=R0%R1, R3 is remainder of R0/R1

BX LR ;return

List DCD Place0,Place1,Place2,Place3 ;pointers to four places

;Assume R2 contains a value from 0 to 3

LDR R1,=List ;R1 points to list of assembly labels

LDR R0,[R1,R2,LSL #2] ;R0 points to code to execute

ORR R0,R0,#1 ;make sure thumb bit set (not needed on Keil)

BX R0 ;jump to place specified by R0

;end of example

Place0 ;code 0

Place1 ;code 1

Place2 ;code 2

Place3 ;code 3

CMN

32-bit Compare Negative

Syntax

CMN{cond} Rn, Op2

where {cond} is an optional condition code. There is no destination register. Rn is the register holding the first operand. Op2 is a flexible second operand. The syntax of Op2 is

CMN Rn, Rm ; op2 = Rm

CMN Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

CMN Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

CMN Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

CMN Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

This instruction compares the value in a register with Op2. They update the condition flags on the result, but do not write the result to a register. The CMN instruction adds the value of Op2 to the value in Rn. The condition codes are set as if a subtraction occurred. This instruction can be followed by a conditional branch.

Rn – (-Op2) (result is calculated but not stored)

This instruction is useful for extending the range of the immediate field of a CMP instruction. E.g.,

CMP R0,#-2 ;not a valid instruction

can be executed as

CMN R0,#2 ;a valid instruction comparing R0 to -2

Restrictions

Do not use PC.
Operand2 must not be SP.

Condition Flags

These instructions update the N, Z, C and V flags according to the result, Rn – (-Op2). R=X-(-M), where X is initial register value, M is the flexible second operand, and R is the final subtracted value.

N: result is negative N = R₃₁

Z: result is zero

V: signed overflow V = X₃₁& M₃₁& (~R₃₁) | (~X₃₁)& (~M₃₁)& R₃₁

C: unsigned overflow C = ~( ((~X₃₁)& (~M₃₁)) | (~M₃₁)& R₃₁ | R₃₁&(~X₃₁) )

Examples

CMN R2, #25 ; compare R2 to -25

BEQ gothere ;branch to gothere if R2 equals -25

CMP

32-bit Compare

Syntax

CMP{cond} Rn, Op2

where {cond} is an optional condition code. There is no destination register. Rn is the register holding the first operand. Op2 is a flexible second operand. The syntax of Op2 is

CMP Rn, Rm ; op2 = Rm

CMP Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

CMP Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

CMP Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

CMP Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

These instructions compare the value in a register with Op2. They update the condition flags on the result, but do not write the result to a register. The CMP instruction subtracts the value of Op2 from the value in Rn. This is the same as a SUBS instruction, except that the result is discarded. This instruction can be followed by a conditional branch.

Rn – Op2 (result is calculated but not stored)

Restrictions

Do not use PC.
Operand2 must not be SP.

Condition Flags

These instructions update the N, Z, C and V flags according to the result, Rn – (Op2). R=X-M, where X is initial register value, M is the flexible second operand, and R is the final subtracted value.

N: result is negative N = R₃₁

Z: result is zero

V: signed overflow

C: unsigned overflow

Examples

CMP R2, #6400

BGT gothere ;branch to gothere if R2>6400 (signed)

CMP R2, R3, LSR #1

BLO gothere ;branch to gothere if R2<(R3>>1) (unsigned)

CPS

Change Processor State

Syntax

CPSIE I ;Clears the Priority Mask Register (PRIMASK)

CPSIE F ;Clears the Fault Mask Register (FAULTMASK)

CPSID I ;Sets the Priority Mask Register (PRIMASK)

CPSID F ;Sets the Fault Mask Register (FAULTMASK)

Operation

CPS changes the PRIMASK and FAULTMASK special register values. See the Data

Sheet for more information about these registers.

Restrictions

Use CPS only from privileged software; it has no effect if used in unprivileged software.
CPS cannot be conditional and so must not be used inside an IT block.

Condition Flags

This instruction does not change the flags.

Examples

CPSID I ; Set I, disable interrupts and configurable fault handlers

CPSIE I ; Clear I, enable interrupts and configurable fault handlers

EOR

32-bit Logical Exclusive OR

Syntax

EOR{S}{cond} {Rd,} Rn, Op2

EOR Rd, Rn, Rm ; op2 = Rm

EOR Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

EOR Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

EOR Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

EOR Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The EOR instruction performs a 32-bit bitwise Exclusive OR operation on the values in Rn and Op2 and places the results into Rd. The EOR instruction is useful for toggling bits. You specify which bits to toggle in the Op2.

Rd = Rn ^ Op2

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Example

TogglePG2

LDR R1, =GPIO_PORTG_DATA_R ;R1 = &GPIO_PORTG_DATA_R

LDR R2, [R1] ;R2 = [R1] (read all data on PG)

EOR R2, R2, #0x04 ;R2 = R2^~0x04 (toggle bit 2)

STR R2, [R1] ;[R1] = R2

BX LR ;return

LDR

Load from memory into a register

Syntax

LDR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset EA=Rn+offset

LDR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed, EA=Rn+offset

LDR{type}{cond} Rt, [Rn], #offset ; post-indexed, EA=Rn

LDR{type}{cond} Rt, [Rn, Rm {, LSL #n}] ; register offset, EA=Rn+(Rm<<n)

LDR{type}{cond} Rt, label ; PC relative, EA=PC+relative

where type is one of

B Unsigned byte, zero extended to 32 bits.
SB Signed byte, sign extended to 32 bits.
H Unsigned halfword, zero extended to 32 bits.
SH Signed halfword, sign extended to 32 bits.
Omit, for word.

{cond} is an optional condition code. Rt is the register to load. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the effective address is the contents of Rn. Rm is a register containing a value to be used as the offset. n is a number 0 to 3.

Operation

LDR instructions copy values from memory into registers. Immediate offset addressing adds the offset value (-255 to 4095) to the value of Rn to get the effective address. The register Rn is unaltered. Pre-indexed addressing first adds the offset (-255 to 255) to Rn to create the effective address. This mode changes Rn. Post-indexed addressing uses the original value of Rn as the effective memory address. After memory is accessed, the offset (-255 to 255) is added to Rn. This mode also changes Rn. Register offset addressing, first shifts left Rm by 0 to 3 bits and adds it to the value of Rn to get the effective address. This mode does not alter Rn or Rm. When using PC-relative addressing, the label must be within -4095 to +4095.

Restrictions

Rt can be SP or PC for word loads only.
Rm must not be SP and must not be PC.
When Rt is PC in a word load instruction, Bit[0] must be 1. If conditional in IT block, it must be last
Rn must not be PC for register offset addressing.

Condition Flags

These instructions do not change the flags.

Examples

LDR R8, [R10] ;Load 32-bit from R10 address to R8

LDRB R0, [R1] ;Load 8-bit unsigned from R1 address to R0

LDRSB R1, [R2,#5] ;Load 8-bit signed from (R2+5) address to R1

LDRH R2, [R5,#2]! ;R5=R5+2, load 16-bit unsigned from R5 address to R2

LDR R3, [R7],#4 ;Load 32-bit from R7 address to R3, R7=R7+4

LDR R0, Pi ;R0=314159

Pi DCD 314159

LSL

32-bit Logical Shift Left

Syntax

LSL{S}{cond} Rd, Rm, Rs

LSL{S}{cond} Rd, Rm, #n

where {S} is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation. {cond} is an optional condition code. Rd is the destination register. Rd can not be omitted. Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte of Rs is used and can be in the range 0 to 255. n is the shift length (0 to 31).

Operation

LSL moves the bits in the register Rm to the left by the number of places specified by constant n or register Rs. This instruction can be used for signed and unsigned integers. Shift left is similar to multiplication by a power of 2. The result is written to Rd, and the value in register Rm remains unchanged.

Rd = Rm << Rs (signed or unsigned)

Rd = Rm << n (signed or unsigned)

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, these instructions update the N and Z flags according to the result in Rd. The C flag is updated to the last bit shifted out, except when the shift length is 0.

N: result is negative N = R₃₁

Z: result is zero

Examples

LSL R7, R8, #9 ;R7 = R8<<9 (similar to R7=R8*512)

LSLS R1, R2, #3 ;R1 = R2<<3 (similar to R1=R2*8) with flag update

LSL R4, R5, R6 ;R4 = R5<<R6 (similar to R4=R5*2^R6)

LSR

32-bit Logical Shift Right

Syntax

LSR{S}{cond} Rd, Rm, Rs

LSR{S}{cond} Rd, Rm, #n

where {S} is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation. {cond} is an optional condition code. Rd is the destination register. Rd cannot be omitted. Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte of Rs is used and can be in the range 0 to 255. n is the shift length (1 to 32).

Operation

LSR moves the bits in the register Rm to the right by the number of places specified by constant n or register Rs. Values are unsigned integers, so zeros are shifted into bit 31. Shift right is similar to unsigned division by a power of 2. The result is written to Rd, and the value in register Rm remains unchanged.

Rd = Rm >> Rs (unsigned)

Rd = Rm >> n (unsigned)

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, these instructions update the N and Z flags according to the result in Rd. The C flag is updated to the last bit shifted out, except when the shift length is 0.

N: result is negative N = R₃₁

Z: result is zero

Examples

LSR R7, R8, #9 ;R7 = R8>>9 (similar to R7=R8/512)

LSRS R1, R2, #3 ;R1 = R2>>3 (similar to R1=R2/8) with flag update

LSR R4, R5, R6 ;R4 = R5>>R6 (similar to R4=R5/2^R6)

MLA

32-bit Multiplication with Accumulation

Syntax

MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate

where {cond} is an optional condition code. Rd is the destination register. Rd cannot be omitted. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added.

Operation

The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least-significant 32 bits of the result in Rd. The result does not depend on whether the operands are signed or unsigned. This instruction is useful for implementing digital filters and other digital signal processing.

Rd = Ra + (Rn * Rm)

Restrictions

Do not use SP and do not use PC.

Condition Flags

This instruction does not change the flags.

Examples

MLA R9, R2, R1, R5 ;R9 = R5 + (R2 * R1)

MLA R0, R2, R3, R0 ;R0 = R0 + (R2 * R3)

MLS

32-bit Multiplication with Subtraction

Syntax

MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract

where {cond} is an optional condition code. Rd is the destination register. Rd cannot be omitted. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be subtracted from.

Operation

The MLS instruction multiplies the values from Rn and Rm, subtracts the product from Ra, and places the least-significant 32 bits of the result in Rd. The result does not depend on whether the operands are signed or unsigned. This instruction is useful for implementing digital filters and other digital signal processing.

Rd = Ra – (Rn * Rm)

Restrictions

Do not use SP and do not use PC.

Condition Flags

This instruction does not change the flags.

Examples

MLS R9, R2, R1, R5 ;R9 = R5 - (R2 * R1)

MLS R0, R2, R3, R0 ;R0 = R0 - (R2 * R3)

MOV

32-bit Move

Syntax

MOV{S}{cond} Rd, Op2

MOV{cond} Rd, #imm16

MOV Rd, Rm ; op2 = Rm

MOV Rd, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

MOV Rd, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

MOV Rd, Rm, ASR #n ; op2 = Rm>>n Rm is signed

MOV Rd, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The MOV instruction copies the value of Op2 into Rd. This instruction is useful for moving values from one register to another, and for initializing registers to a constant value.

Rd = Op2

Restrictions

You can use SP and PC, with the following restrictions:

The second operand must be a register without shift
You must not specify the S suffix.

Though it is possible to use MOV as a branch instruction, it is strongly recommended the use BX or BLX.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Examples

MOVS R11, #10 ; R11=10, N and Z flags get updated

MOV R1, #0xFA05 ; R1 = 0xFA05

MOVS R10, R12 ; R10 = R12, N and Z flags get updated

MOVS R0, R0 ; N and Z flags set according to R0

MOV R11, SP ; Place a copy of stack pointer in R11

MOVEQ R0, #0 ; Part of IT, if Z=1, set R0=0

MUL

32-bit Multiplication

Syntax

MUL{S}{cond} {Rd,} Rn, Rm ; Multiply

Operation

The MUL instruction multiplies the values from Rn and Rm, and places the least-significant 32 bits of the result in Rd. The result does not depend on whether the operands are signed or unsigned. This instruction is useful for implementing digital filters and other digital signal processing.

Rd = Rn * Rm

Restrictions

In these instructions, do not use SP and do not use PC. If you use the S suffix:

Rd, Rn, and Rm must all be in the range R0 to R7.
Rd must be the same as Rm.
You must not use the cond suffix.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It does not affect the C and V flags.

N: result is negative N = R₃₁

Z: result is zero

Examples

MUL R10, R2, R5 ;R10 = R2 * R5

MUL R0, R1 ;R0 = R0 * R1

MULS R0, R1 ;R0 = R0 * R1, sets N and Z flags

MULCC R2, R3, R2 ;part of IT, if C=0, R2 = R3 x R2

MVN

32-bit Move NOT

Syntax

MVN{S}{cond} Rd, Op2

MVN Rd, Rm ; op2 = Rm

MVN Rd, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

MVN Rd, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

MVN Rd, Rm, ASR #n ; op2 = Rm>>n Rm is signed

MVN Rd, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The MVN instruction takes the value of Op2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

Rd = ~Op2

This instruction is useful for extending the range of the immediate field of a MOV instruction. For example

MOV R0,#-2 ;not a valid instruction (-2 = 0xFFFF.FFFE)

can be executed as

MVN R0,#1 ;R0 = -2

Restrictions

You cannot use SP and PC

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Examples

MVN R0, #10 ;R0 = -11

MVN R1, R2 ;R1 = ~R2

MVN R1, R2, LSL #2 ;R1 = ~(R2<<2)

ORN

32-bit Logical OR NOT

Syntax

ORN{S}{cond} {Rd,} Rn, Op2

ORN Rd, Rn, Rm ; op2 = Rm

ORN Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

ORN Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

ORN Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

ORN Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The ORN instruction performs a 32-bit bitwise OR operation on the bits in Rn with the complements of the corresponding bits in Op2 and places the results into Rd. The ORN extends the useful range of the OR.

Rd = Rn | ~Op2

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Examples

ORN R9, R2, #0x00FF ;R9 = R2 | 0xFFFFFF00

ORN R7, R11, R12, LSR #4 ;R7 = R11 | (~(R12>>2)), R12 is unsigned

ORR

32-bit Logical OR

Syntax

ORR{S}{cond} {Rd,} Rn, Op2

ORR Rd, Rn, Rm ; op2 = Rm

ORR Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

ORR Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

ORR Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

ORR Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The OR instruction performs a 32-bit bitwise OR operation on the values in Rn and Op2 and places the results into Rd. The OR instruction is useful for setting bits. You specify which bits to set in the Op2.

Rd = Rn | Op2

Restrictions

Do not use SP and do not use PC.

Condition Flags

If S is specified, update the N and Z flags according to the result, Rd. It can also update the C flag during the calculation of Op2. It does not affect the V flag.

N: result is negative N = R₃₁

Z: result is zero

Examples

ORR R9, R2, #0xFF00 ;R9 = R2 | 0xFF00 (set bits 15-8)

ORREQ R2, R0, R5 ;part of IT, if Z=1, R2=R0|R5

ORRS R7, R11, #0x18181818 ;R7=R11|0x18181818

POP

Pop registers off a full-descending stack

Syntax

POP{cond} reglist

where {cond} is an optional condition code. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. POP is a synonym for LDM with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. According to AAPCS we need to push and pop an even number of registers to maintain an 8-byte alignment on the stack.

Operation

POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address.

Restrictions

reglist must not contain SP.
reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:

Bit[0] of the value loaded to the PC must be 1 for correct execution,
A branch occurs to this halfword-aligned address.

If the instruction is conditional, it must be the last instruction in the IT block.

Condition Flags

This instruction does not change the flags.

Examples

POP {R5} ;pop 32 bits from stack and place it in R5

POP {R0,R4-R7} ;pop 5 words from stack and place into R0,R4,R5,R6,R7

POP {R2,LR} ;pop 2 words from stack and place into R2, R14

POP {R0,R10,PC} ;pop 3 words from stack and place into R0,R10,PC

;example subroutine

Func PUSH {R4-R8,LR} ;save registers

;body of subroutine

POP {R4-R8,PC} ;restore registers and return

PUSH

Push registers onto a full-descending stack

Syntax

PUSH{cond} reglist

where {cond} is an optional condition code. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. PUSH is a synonym for STMDB with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. According to AAPCS we need to push and pop an even number of registers to maintain an 8-byte alignment on the stack.

Operation

PUSH stores registers on the stack in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address.

Restrictions

reglist must not contain SP or PC
If the instruction is conditional, it must be the last instruction in the IT block.

Condition Flags

This instruction does not change the flags.

Examples

PUSH {R0} ;push the 32-bit contents of R0 on stack

PUSH {R0,R4-R7} ;push R7,R6,R5,R4,R0 on stack (R0 on top)

PUSH {R2,LR} ;push LR,R2 on stack (R2 on top)

;example subroutine, with local variable

Func PUSH {R4-R8,LR} ;save registers

sum EQU 0 ;32-bit local variable, stored on the stack

MOV R0,#0

PUSH {R0,R1} ;allocate and initialize 2 local variables

;body of subroutine

LDR R1,[SP,#sum] ;R1=sum

ADD R1,R0 ;R1=R0+sum

STR R1,[SP,#sum] ;sum=R0+sum

;end of subroutine

ADD SP,#8 ;deallocate sum

POP {R4-R8,PC} ;restore registers and return

RSB

32-bit Reverse Subtraction

Syntax

RSB{S}{cond} {Rd,} Rn, Op2

RSB Rd, Rn, Rm ; op2 = Rm

RSB Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

RSB Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

RSB Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

RSB Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The RSB instruction subtracts the value in Rn from the value of Op2 and stores the sum in Rd.

Rd = Op2 - Rn

This is useful because of the wide range of options for Op2.

Restrictions (for additional restrictions about PC see data sheet)

Op2 must not be SP and must not be PC.
Rn cannot be SP.

Condition Flags

If S is specified, these instructions update the N, Z, C and V flags according to the result. R=M-X, where X is initial register value, M is the flexible second operand, and R is the final register value.

N: result is negative N = R₃₁

Z: result is zero

V: signed overflow V = M₃₁& (~X₃₁)& (~R₃₁) | (~M₃₁)&X₃₁& R₃₁

C: unsigned overflow C = ~( (~M₃₁& X₃₁ ) | X₃₁& R₃₁ | R₃₁&(~M₃₁) )

Examples

RSB R2, R1, R3 ;R2=R3-R1

RSBS R8, R6, #240 ;R8=240-R6, sets the flags

RSB R4, R4, #1280 ;R4=1280-R4

RSB R0, R0, #0 ;R0= 0-R0, negate

RSB R1, R1, R1, LSL #3 ;R1= 8*R1-R1 = 7*R1

SDIV

32-bit Signed Division

Syntax

SDIV{cond} {Rd,} Rn, Rm

where {cond} is an optional condition code. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be dividend. Rm is a register holding the divisor.

Operation

SDIV performs a signed integer division of the value in Rn by the value in Rm. If the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.

Rd = Rn / Rm

Restrictions

Do not use SP and do not use PC.

Condition Flags

This instruction does not change the flags.

Examples

SDIV R0, R2, R4 ;Signed divide, R0 = R2/R4.

SDIV R8, R1 ;Signed divide, R8 = R8/R1.

; find the signed quotient and remainder of R0 divided by R1

; Inputs: dividend in R0

; divisor in R1

; Outputs: quotient in R2

; remainder in R3

;dividend = divisor*quotient + remainder

;remainder has the same sign as dividend

Divide

SDIV R2,R0,R1 ;R2=R0/R1, R2 is quotient

MUL R3,R2,R1 ;R3=(R0/R1)*R1

SUB R3,R0,R3 ;R3=R0%R1, R3 is remainder of R0/R1

BX LR ;return

STR

Store from register into memory

Syntax

STR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset EA=Rn+offset

STR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed, EA=Rn+offset

STR{type}{cond} Rt, [Rn], #offset ; post-indexed, EA=Rn

STR{type}{cond} Rt, [Rn, Rm {, LSL #n}] ; register offset, EA=Rn+(Rm<<n)

where type is one of

B Unsigned byte, save bits 7-0 into memory.
H Unsigned halfword, save bits 15-0 into memory.
Omit, for word.

{cond} is an optional condition code. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the effective address is the contents of Rn. Rm is a register containing a value to be used as the offset. n is a number 0 to 3.

Operation

STR instructions copy 8-bit 16-bit or 32-bit values from registers to memory. Immediate offset addressing adds the offset value (-255 to 4095) to the value of Rn to get the effective address. The register Rn is unaltered. Pre-indexed addressing first adds the offset (-255 to 255) to Rn to create the effective address. This mode changes Rn. Post-indexed addressing uses the original value of Rn as the effective memory address. After memory is accessed, the offset (-255 to 255) is added to Rn. This mode also changes Rn. Register offset addressing, first shifts left Rm by 0 to 3 bits and adds it to the value of Rn to get the effective address. This mode does not alter Rn or Rm.

Restrictions

Rt can be SP for word stores only.
Rt must not be PC.
Rm must not be SP and must not be PC.
Rn must not be PC.

Condition Flags

These instructions do not change the flags.

Examples

STR R2, [R9,#4] ;32-bit store value of R2 into address R9+4

STRH R3, [R4], #2 ;16-bit store value of R3 into address R4, R4=R4+2

STRB R0, [R5, R1] ;8-bit store value of R0 into address R5+R1

STRH R0, [R5, R1, LSL #1] ;16-bit store R0 into address R5+2*R1

STR R0, [R1, R2, LSL #2] ;32-bit store R0 into address R1+4*R2

STRB R0, [R5, #1]! ;R5=R5+1,8-bit store value of R0 into address R5

SUB

32-bit Subtraction

Syntax

SUB{S}{cond} {Rd,} Rn, Op2

SUB{cond} {Rd,} Rn, #imm12

SUB Rd, Rn, Rm ; op2 = Rm

SUB Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned

SUB Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned

SUB Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed

SUB Rd, Rn, #constant ; op2 = constant, where X and Y are hexadecimal digits:

· produced by shifting an 8-bit unsigned value left by any number of bits

· in the form 0x00XY00XY

· in the form 0xXY00XY00

· in the form 0xXYXYXYXY

Operation

The SUB instruction subtracts the value of Op2 or imm12 from the value in Rn and stores the sum in Rd. This instruction can be followed by a conditional branch.

Rd = Rn - Op2

Rd = Rn - imm12

Restrictions (for additional restrictions about PC see data sheet)

Op2 must not be SP and must not be PC.
Rd can be SP only with the additional restrictions:

Rn must also be SP.
any shift in Op2 must be limited to a maximum of 3 bits using LSL.

Condition Flags

N: result is negative N = R₃₁

Z: result is zero

V: signed overflow

C: unsigned overflow

Examples

SUB R2, R1, R3 ;R2=R1-R3

SUBS R6, #240 ;R6=R6-240, sets the flags on the result

UDIV

32-bit Unsigned Division

Syntax

UDIV{cond} {Rd,} Rn, Rm

Operation

UDIV performs an unsigned integer division of the value in Rn by the value in Rm. If the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.

Rd = Rn / Rm

Restrictions

Do not use SP and do not use PC.

Condition Flags

This instruction does not change the flags.

Examples

UDIV R0, R2, R4 ;Signed divide, R0 = R2/R4.

UDIV R8, R1 ;Unsigned divide, R8 = R8/R1.

; find the unsigned quotient and remainder

; Inputs: dividend in R0

; divisor in R1

; Outputs: quotient in R2

; remainder in R3

;dividend = divisor*quotient + remainder

Divide

UDIV R2,R0,R1 ;R2=R0/R1, R2 is quotient

MUL R3,R2,R1 ;R3=(R0/R1)*R1

SUB R3,R0,R3 ;R3=R0%R1, R3 is remainder of R0/R1

BX LR ;return

Reprinted with approval from Introduction to Embedded Systems, 2022, ISBN: 978-1537105727