// Timer0A.c // Runs on LM3S1968 // Use Timer0A in periodic mode to request interrupts at a particular // period. // Daniel Valvano // September 14, 2011 /* This example accompanies the book "Embedded Systems: Real Time Interfacing to the Arm Cortex M3", ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2011 Program 7.5, example 7.6 Copyright 2011 by Jonathan W. Valvano, valvano@mail.utexas.edu You may use, edit, run or distribute this file as long as the above copyright notice remains THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. For more information about my classes, my research, and my books, see http://users.ece.utexas.edu/~valvano/ */ #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable #define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) // IRQ 0 to 31 Set Enable Register #define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) // IRQ 16 to 19 Priority Register #define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000)) #define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004)) #define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C)) #define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018)) #define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020)) #define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024)) #define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028)) #define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038)) #define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048)) #define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration, // function is controlled by bits // 1:0 of GPTMTAMR and GPTMTBMR #define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode #define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA Enable #define TIMER_IMR_TATOIM 0x00000001 // GPTM TimerA Time-Out Interrupt // Mask #define TIMER_ICR_TATOCINT 0x00000001 // GPTM TimerA Time-Out Raw // Interrupt #define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load // Register Low #define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104)) #define SYSCTL_RCGC1_TIMER0 0x00010000 // timer 0 Clock Gating Control void DisableInterrupts(void); // Disable interrupts void EnableInterrupts(void); // Enable interrupts long StartCritical (void); // previous I bit, disable interrupts void EndCritical(long sr); // restore I bit to previous value void WaitForInterrupt(void); // low power mode void (*PeriodicTask)(void); // user function // ***************** Timer0A_Init **************** // Activate Timer0A interrupts to run user task periodically // Inputs: task is a pointer to a user function // period in usec // Outputs: none void Timer0A_Init(void(*task)(void), unsigned short period){ SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0; // 0) activate timer0 PeriodicTask = task; // user function TIMER0_CTL_R &= ~0x00000001; // 1) disable timer0A during setup TIMER0_CFG_R = 0x00000004; // 2) configure for 16-bit timer mode TIMER0_TAMR_R = 0x00000002; // 3) configure for periodic mode TIMER0_TAILR_R = period; // 4) reload value TIMER0_TAPR_R = 49; // 5) 1us timer0A TIMER0_ICR_R = 0x00000001; // 6) clear timer0A timeout flag TIMER0_IMR_R |= 0x00000001; // 7) arm timeout interrupt NVIC_PRI4_R = (NVIC_PRI4_R&0x00FFFFFF)|0x40000000; // 8) priority 2 NVIC_EN0_R |= NVIC_EN0_INT19; // 9) enable interrupt 19 in NVIC TIMER0_CTL_R |= 0x00000001; // 10) enable timer0A EnableInterrupts(); } void Timer0A_Handler(void){ TIMER0_ICR_R = TIMER_ICR_TATOCINT;// acknowledge timer0A timeout (*PeriodicTask)(); // execute user task }